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1.1. Generating the Design Example
1.2. Directory Structure
1.3. Simulating the Design Example Testbench
1.4. Compiling and Configuring the Design Example in Hardware
1.5. Changing Target Device in Hardware Design Example
1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
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1.3. Simulating the Design Example Testbench
You can compile and simulate the design by running a simulation script from the command prompt.
- At the command prompt, change the working directory to <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
Table 3. Instructions to Simulate the Testbench Simulator Instructions ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition In the command line, type:vsim -do run_vsim.do
If you prefer to simulate without bringing up the GUI, type:vsim -c -do run_vsim.do
VCS* In the command line, type sh run_vcs.sh VCS* MX In the command line, type sh run_vcsmx.sh. Use this script when the design contains Verilog HDL and System Verilog with VHDL.
NCSim In the command line, type sh run_ncsim.sh Xcelium* In the command line, type sh run_xcelium.sh
A successful simulation ends with the following message:
Simulation Passed.or
Testbench complete.After successful completion, you can analyze the results.