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Ixiasoft
1.1. Generating the Design Example
1.2. Directory Structure
1.3. Simulating the Design Example Testbench
1.4. Compiling and Configuring the Design Example in Hardware
1.5. Changing Target Device in Hardware Design Example
1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
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Ixiasoft
2.5.1. Internal Loopback Test
Run these steps to perform the internal loopback test:
- Reset the system.
sys_reset_digital_analog
- Display the clock frequency and PHY status.
chkphy_status
- Turn on the internal loopback test.
loop_on
- Display the clock frequency and PHY status. The rx_clk is set to 312.5 MHz and rx_pcs_ready is set to 1.
chkphy_status
- Start the packet generator.
start_pkt_gen
- Stop the packet generator.
stop_pkt_gen
- Review the number of transmitted and received packets.
chkmac_stats
- Tun off the internal loopback test.
loop_off