Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 683747
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide

3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.12 24.2 22.2.0
  • Updated the product family name to "Intel Agilex 7."
  • Updated instructions for ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition simulators in Table: Instructions to Simulate the Testbench.
  • Updated description for run_vsim.do filename in Table: Low Latency E-Tile 40G Ethernet Core Testbench File Descriptions.
2020.06.22 20.2 20.0.0 Added device support for Intel Agilex devices.
2020.04.13 20.1 19.1.0 Initial Release.
Level Two Title