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1.1. Generating the Design Example
1.2. Directory Structure
1.3. Simulating the Design Example Testbench
1.4. Compiling and Configuring the Design Example in Hardware
1.5. Changing Target Device in Hardware Design Example
1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
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2. Design Example Description
The E-tile based 40G Ethernet design example demonstrates the functions of the Low Latency E-Tile 40G Ethernet Intel® FPGA IP core, with E-tile based transceiver interface compliant with the IEEE 802.3ba standard CAUI-4 specification. You can generate the design from the Example Design tab in the Low Latency E-Tile 40G Ethernet Intel® FPGA IP parameter editor.
To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench and hardware design example use this variation as the DUT. If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.
Note: The testbench demonstrates a basic test of the IP core. It is not intended to be a substitute for a full verification environment. You must perform more extensive verification of your own Low Latency E-Tile 40G Ethernet Intel® FPGA IP design in simulation and in hardware.