Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab Status Port PMA Setting Data Type Error Control Loopback 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

6.3.6. The PCIe Tab

This tab allows you to run a PCIe* loopback test on your board. You can also load the design and use an oscilloscope to measure an eye diagram of the PCIe* transmit signals.

Figure 25. The PCIe Tab

The following sections describe the controls on the PCIe* tab.

Status

Displays the following status information during a loopback test:
  • PLL Lock: Shows the PLL locked or unlocked state.
  • Pattern sync: Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.
  • Details: Shows the PLL lock and pattern sync status:

Port

PCIe* x16 Gen3

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:
  • Serial Loopback: Routes signals between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • 1st pre: Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
    • 2nd pre: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • 1st post: Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
    • 2nd post: Specifies the amount of pre-emphasis on the second post tap of the transmitter buffer.
  • Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage mode.
  • DC gain: Specifies the DC gain setting for the receiver equalizer in four stage mode.
  • VGA: Specifies the VGA gain value.
  • All PMA settings should be changed as given in the figure below:
    Figure 26. PMA Settings

Data Type

Specifies the type of data contained in the transactions. The following data types are available for analysis:
  • PRBS 7: Selects pseudo-random 7-bit sequences.
  • PRBS 15: Selects pseudo-random 15-bit sequences.
  • PRBS 23: Selects pseudo-random 23-bit sequences.
  • PRBS 31: Selects pseudo-random 31-bit sequences.
  • HF: Selects highest frequency divide-by-2 data pattern 10101010.
  • LF: Selects lowest frequency divide-by-33 data pattern.

Error Control

Displays data errors detected during analysis and allows you to insert errors:
  • Detected errors: Displays the number of data errors detected in the hardware.
  • Inserted errors: Displays the number of errors inserted into the transmit data stream.
  • Insert error: Inserts a one-word error into the transmit data stream each time you click the button. Insert error is only enabled during transaction performance analysis.
  • Clear: Resets the detected errors and inserted errors counters to zeroes.

Loopback

  • Start: Initiates the selected ports transaction performance analysis.
    Note: Always click Clear before Start
  • Stop: Terminates transaction performance analysis.
  • TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
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