Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.6.1. PCI Express

The Intel® Stratix® 10 GX FPGA development board is designed to fit entirely into a PC motherboard with a x16 PCI Express* slot that can accommodate a full height, 3-slot long form factor add-in card. This interface uses the Intel® Stratix® 10 GX FPGA's PCI Express* hard IP block, saving logic resources for the user logic application. The PCI Express* edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.

The PCI Express* interface supports auto-negotiating channel width from x1 to x4 to x8 to x16 by using Intel's PCIe* Intel® FPGA IP. You can also configure this board to a x1, x4, x8 or x16 interface through a DIP switch that connects the PRSTn pins for each bus width.

The PCI Express* edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen1), 5.0 Gbps/lane for maximum of 80 Gbps full-duplex (Gen 2), or 8.0 Gbps/lane for a maximum of 128 Gbps full-duplex (Gen3).

The power for the board can be sourced entirely from the PC host when installed into a PC motherboard with the PC's 2x3 and 2x4 ATX auxiliary power connected to the 12V ATX inputs (J26 and J27) of the Intel® Stratix® 10 development board. Although the board can also be powered by a laptop power supply for use on a lab bench, Intel recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.

The PCIE_EDGE_REFCLK_P/N signal is a 100 MHz differential input that is driven from the PC motherboard onto this board through the edge connector. This signal connects directly to a Intel® Stratix® 10 GX FPGA REFCLK input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL). The JTAG and SMB are optional signals in the PCI Express* TDI to PCI Express* TDO and are not used on this board. The SMB signals are wired to the Intel® Stratix® 10 GX FPGA but are not required for normal operation.

Table 16.  PCI Express Pin Assignments, Schematic Signal Names and Functions
Receive bus Schematic Signal Name FPGA Pin Number I/O Standard Description
A11 PCIE_EDGE_PERSTn - 3V LVCMOS Reset
A14 PCIE_EDGE_REFCLK_N AK40 LVDS Motherboard reference clock
A13 PCIE_EDGE_REFCLK_P AK41 LVDS Motherboard reference clock
B5 PCIE_EDGE_SMBCLK - 1.8V SMB clock
B6 PCIE_EDGE_SMBDAT - 1.8V SMB data
A1 PCIE_PRSNT1n – – Link with DIP switch (SW2)
B17 PCIE_PRSNT2n_X1 – – Link with DIP switch (SW2)
B31 PCIE_PRSNT2n_X4 – – Link with DIP switch (SW2)
B48 PCIE_PRSNT2n_X8 – – Link with DIP switch (SW2)
B81 PCIE_PRSNT2n_X16 – – Link with DIP switch (SW2)
B15 PCIE_RX_N0 BH40 1.4 V PCML Receive bus
B20 PCIE_RX_N1 BJ42 1.4 V PCML Receive bus
B24 PCIE_RX_N2 BG42 1.4 V PCML Receive bus
B28 PCIE_RX_N3 BE42 1.4 V PCML Receive bus
B34 PCIE_RX_N4 BC42 1.4 V PCML Receive bus
B38 PCIE_RX_N5 BD44 1.4 V PCML Receive bus
B42 PCIE_RX_N6 BA42 1.4 V PCML Receive bus
B46 PCIE_RX_N7 BB44 1.4 V PCML Receive bus
B51 PCIE_RX_N8 AW42 1.4 V PCML Receive bus
B55 PCIE_RX_N9 AY44 1.4 V PCML Receive bus
B59 PCIE_RX_N10 AU42 1.4 V PCML Receive bus
B63 PCIE_RX_N11 AV44 1.4 V PCML Receive bus
B67 PCIE_RX_N12 AR42 1.4 V PCML Receive bus
B71 PCIE_RX_N13 AT44 1.4 V PCML Receive bus
B75 PCIE_RX_N14 AP44 1.4 V PCML Receive bus
B79 PCIE_RX_N15 AN42 1.4 V PCML Receive bus
B14 PCIE_RX_P0 BH41 1.4 V PCML Receive bus
B19 PCIE_RX_P1 BJ43 1.4 V PCML Receive bus
B23 PCIE_RX_P2 BG43 1.4 V PCML Receive bus
B27 PCIE_RX_P3 BE43 1.4 V PCML Receive bus
B33 PCIE_RX_P4 BC43 1.4 V PCML Receive bus
B37 PCIE_RX_P5 BD45 1.4 V PCML Receive bus
B41 PCIE_RX_P6 BA43 1.4 V PCML Receive bus
B45 PCIE_RX_P7 BB45 1.4 V PCML Receive bus
B50 PCIE_RX_P8 AW43 1.4 V PCML Receive bus
B54 PCIE_RX_P9 AY45 1.4 V PCML Receive bus
B58 PCIE_RX_P10 AU43 1.4 V PCML Receive bus
B62 PCIE_RX_P11 AV45 1.4 V PCML Receive bus
B66 PCIE_RX_P12 AR43 1.4 V PCML Receive bus
B70 PCIE_RX_P13 AT45 1.4 V PCML Receive bus
B74 PCIE_RX_P14 AP45 1.4 V PCML Receive bus
B78 PCIE_RX_P15 AN43 1.4 V PCML Receive bus
B11 PCIE_WAKEn_R AU34 1.8V Wake Signal
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