Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.6.6. I2C

I2C supports communication between integrated circuits on a board. It is a simple two-wire bus that consists of a serial data line (SDA) and a serial clock (SCL). The MAX® V and the Intel® Stratix® 10 devices use the I2C for reading and writing to the various components on the board such as programmable clock generators, VID regulators, ADC and temperature sensors.

You can use the Intel® Stratix® 10 or MAX® V as the I2C host to access these devices, change clock frequencies or get board status information such as voltage and temperature readings.

Figure 10. I2C Block Diagram
Table 21.  MAX V I2C Signals
Schematic Signal Name MAX® V Pin Number I/O Standard Description
I2C_1.8V_SCL P13 1.8V

I2C serial clock from MAX® V

I2C_1.8V_SDA R14 1.8V

I2C serial data from MAX® V

Table 22.   Intel® Stratix® 10 FPGA I2C Signals
Schematic Signal Name Intel® Stratix® 10 FPGA Pin Number I/O Standard Description
LT_1.8V_SCL BG22 1.8V

Intel® Stratix® 10 FPGA I2C from SDM IO pin (default)

LT_1.8V_SDA BF22 1.8V

Intel® Stratix® 10 FPGA I2C from SDM IO pin (default)

LT_IO_SCL V21 1.8V

Intel® Stratix® 10 FPGA I2C from GPIO pin

LT_IO_SDA V22 1.8V

Intel® Stratix® 10 FPGA I2C from GPIO pin

Table 23.   Intel® Stratix® 10 FPGA I2C Signals to Intel® FPGA Download Cable II
Schematic Signal Name Intel® Stratix® 10 FPGA Pin Number I/O Standard Description
USB_SCL AB12 3.0V

Dedicated I2C to Intel® FPGA Download Cable II

USB_SDA AF17 3.0V

Dedicated I2C to Intel® FPGA Download Cable II

Table 24.   Intel® Stratix® 10 FPGA I2C Signals to QSFP module
Schematic Signal Name Intel® Stratix® 10 FPGA Pin Number I/O Standard Description
QSFP_SCL BJ26 1.8V

Dedicated I2C to QSFP module

QSFP_SDA BH27 1.8V

Dedicated I2C to QSFP module

Table 25.   Intel® Stratix® 10 FPGA I2C Signals to FMC Connector
Schematic Signal Name Intel® Stratix® 10 FPGA Pin Number FMC Connector Pin Number I/O Standard Description
FMCA_SCL BH21 C30 1.8V

Dedicated I2C to FMC Connector

FMCA_SDA BH20 C31 1.8V

Dedicated I2C to FMC Connector

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