Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

6.2. Running the Board Test System

Before you begin

With the power to the board off, follow these steps:
  1. Connect the USB cable to your PC and the board.
  2. Ensure that the Ethernet patch cord is plugged into the RJ-45 connector.
  3. Check whether the development board switches and jumpers are set according to your preferences.
  4. Set the load selector switch (SW3.3) to OFF for user hardware1 (page#1). The development kit ships with the CFI Flash device preprogrammed with a default:
    • Factory FPGA configuration for running the Board Update Portal design example
    • User configuration for running the BTS demonstration
  5. Turn on the power to the board. The board loads the design stored in the user hardware1 portion of flash memory into the FPGA. If your board is still in the factory configuration, or if you have downloaded a newer version of the BTS to the flash memory through the Board Update Portal, the design loads the GPIO, Ethernet and flash memory tests.
Note: To ensure operating stability, keep the USB cable connected and the board powered on when running the demonstration application. The BTS cannot run correctly unless the USB cable is attached and the board is on.

To run the BTS

  1. Navigate to the <package dir>\examples\board_test_system directory and run the BoardTestSystem.exe application.
  2. A GUI appears, displaying the application tab corresponding to the design running in the FPGA. If the design loaded in the FPGA is not supported by the BTS GUI, you receive a message prompting you to configure your board with a valid BTS design. Refer to the Configure Menu on configuring your board.
Note: If some design is running in the FPGA, the BTS GUI loads the design file (.sof) in the image folder to check the current running design in the FPGA; therefore the design running in the FPGA must be the same as the design file in the image folder.
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