Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.1. Board Overview

An image of the Intel® Stratix® 10 GX FPGA development board is shown below.
Figure 4.  Intel® Stratix® 10 GX FPGA Development Board Image - Front
Figure 5.  Intel® Stratix® 10 GX FPGA Development Board Image - LED Daughter Board Close Up
Figure 6.  Intel® Stratix® 10 GX FPGA Development Board Image - Rear
Table 10.   Intel® Stratix® 10 GX FPGA Development Board Components
Board Reference Type Description
Featured Devices
U1 FPGA

Intel® Stratix® 10 GX FPGA, 1SG280LU3F50E3VGS1.

  • Adaptive logic modules (ALMs): 933,120
  • LEs (K): 2,753
  • Registers: 3,732,480
  • M20K memory blocks: 11,721
  • Transceiver Count: 96
  • Package Type: 2397 BGA
U11 CPLD MAX® V CPLD, 2210 LEs, 256 FBGA, 1.8V VCCINT.
Configuration and Setup Elements
CN1 On-board Intel® FPGA Download Cable II Micro-USB 2.0 connector for programming and debugging the FPGA.
SW2 PCI Express* Control DIP Switch Enables PCI Express* link widths x1, x4, x8 and x16.
SW6 JTAG Bypass DIP Switch Enables and disables devices in the JTAG chain. This switch is located on the back of the board.
SW1 MSEL Configuration DIP Switch Sets the Intel® Stratix® 10 MSEL pins.
SW3 Board settings DIP Switch Controls the MAX® V CPLD System Controller functions such as clock reset, clock enable, factory or user design load from flash and FACTORY signal command sent at power up. This switch is located at the bottom of the board.
S4 CPU reset push button The default reset for the FPGA logic. This button resides on the LED daughter board.
S2 Image select push button Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA. This button resides on the LED daughter board.
S1 Program configuration push button Configures the FPGA from flash memory image based on the program LEDs. This button resides on the LED daughter board.
S3 MAX® V reset push button The default reset for the MAX® V CPLD System Controller. This button resides on the LED daughter board.
Status Elements
D14, D16 JTAG LEDs Indicates the transmit or receive activity of the System Console USB interface. The TX and RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle. These LEDs reside on the LED daughter board.
D18, D21 System Console LEDs Indicates the transmit or receive activity of the System Console USB interface. The TX and RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle.
D1, D2, D5 Program LEDs Illuminates to show the LED sequence that determines which flash memory image loads to the FPGA when you press the program load push button. The LEDs reside on the LED daughter card.
D8 Configuration Done LED Illuminates when the FPGA is configured. This LED resides on the LED daughter board.
D6 Load LED Illuminates during FPGA configuration. This LED resides on the LED daughter board.
D3 Error LED Illuminates when the FPGA configuration fails. This LED resides on the LED daughter board.
D45 Power LED Illuminates when the board is powered on.
D40 Temperature LED Illuminates when an over temperature condition occurs for the FPGA device. Ensure that an adequate heatsink/fan is properly installed.
D2, D3, D4, D5, D6 Ethernet LEDs Shows the connection speed as well as transmit or receive activity.
D9 SDI Cable LED Illuminates to show the transmit or receive activity for the SDI interface.
D15, D17, D19, D20, D22, D23 PCI Express* link LEDs You can configure these LEDs to display the PCI Express* link width (x1, x4, x8 and x16) and data rate (Gen2, Gen3). These LEDs reside on the LED daughter board.
D4, D7, D9, D10 User defined LEDs Four bi-color LEDs (green and red) for 8 user LEDs. Illuminates when driven low. These LEDs reside on the LED daughter board.
D11, D12, D13 FMC LEDs Illuminates for RX, TX, PRNSTn activity of the FMC daughter card (when present). These LEDs reside on the LED daughter board.
Clock Circuits
X1 SDI Reference Clock

SW4.2 DIP switch controlled:

FS=0: 148.35 MHz

FS=1: 148.5 MHz
U7 Programmable Clock Generator

Si 5341A Programmable Clock Generator by the clock control GUI

Default Frequencies are
  • Out0=155.25 MHz
  • Out1=644.53125 MHz
  • Out2= 135 MHz
  • Out3= Not Used
  • Out4=156.25 MHz
  • Out5= 625 MHz
  • Out6=Not used
  • Out7=125 MHz
  • Out8= 125 MHz
  • Out9=125 MHz
U9 Programmable Clock Generator

Si5338A Programmable Clock Generator by the clock control GUI.

Default frequencies are:
  • CLK0= 100 MHz
  • CLK1= 100 MHz
  • CLK2= 133 MHz
  • CLK3= 50 MHz
J3, J4 Clock input MMPX connector MMPX clock input for the SDI interface.
J1, J2 MMPX GPIO/CLK output from FPGA Bank 3I MMPX GPIO/CLK output from FPGA Bank 3I.
J17, J18 Serial Digital Interface (SDI) transceiver connectors Two HDBNC connectors. Drives serial data input/output to or from SDI video port.
Transceiver Interfaces
J9 PCIe* x16 gold fingers PCIe* TX/RX x16 interface from FPGA bank 1C, 1D and 1E.
J12 Mini Display Port Video Connector Four TX channels of Display Port Video interface from FPGA Bank 1F.
J15 QSFP connector Four TX/RX channels from FPGA Bank 1K
J17, J18 SDI HDBNC Video Connector Single TX/RX channel from FPGA bank 1N.
J13 Intel FMC Interface Sixteen TX/RX channels from FPGA banks 4C, 4D and 4E.
General User Input/Output
SW1 FPGA User DIP Switch Four user DIP switches. When switch is ON, a logic 0 is selected. This switch resides on the LED daughter board.
S5, S6, S7 General user push buttons Three user push buttons. Driven low when pressed. These buttons reside on the LED daughter board.
D4, D7, D9, D10 User defined LEDs Four bi-color user LEDs. Illuminates when driven low. These LEDs reside on the LED daughter board.
Memory Devices
J11 HiLo Connector

One x72 memory interface supporting DDR3 (x72), DDR4 (x72), QDR4 (x36) and RLDRAM3 (x36).

This development kit includes three plugin modules (daughtercards) that use the HiLo connector:
  • DDR4 memory (x72) 1333 MHz
  • DDR3 memory (x72) 1066 MHz
  • RLDRAM3 memory (x36) 1200 MHz
U12, U83 Flash Memory ICS-1GBIT STRATA FLASH, 16-BIT DATA.
Communication Ports
J9 PCI Express* x16 edge connector Gold-plated edge fingers for up to x16 signaling in either Gen1, Gen2 or Gen3 mode.
J13 FMC Port FPGA mezzanine card ports
J10 Gbps Ethernet RJ-45 connector RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Intel Triple Speed Ethernet MAC Intel® FPGA IP core function in SGMII mode.
J15 QSFP Interface Provides four transceiver channels for a 40G/100G QSFP module.
CN1 Micro-USB connector Embedded Intel Intel® FPGA Download Cable II JTAG for programming the FPGA via a USB cable.
Display Ports
J12 Mini DisplayPort Connector Mini DisplayPort male receptacle.
J17, J18 SDI video port Two HDBNC connectors that provide a full-duplex SDI interface.
Power Supply
J9 PCI Express* edge connector Interfaces to a PCI Express* root port such as an appropriate PC motherboard.
J27 DC input jack Accepts a 12 V DC power supply when powering the board from the provided power brick for lab bench operation. When operating from the PCIe* slot, this input must also be connected to the 6-pin Aux PCIe* power connector provided by the PC system along with J27, or else the board does not power on.
SW7 Power switch Switch to power ON or OFF the board when supplied from the DC input jack.
J26 PCIe* 2x4 ATX power connector 12 V ATX input. This input must be connected to the 8-pin Aux PCIe* power connector provided by the PC system when the board is plugged into a PCIe* slot, or else the board does not power on.
Level Two Title