Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.8.1. Flash

The Intel® Stratix® 10 GX FPGA development board supports two 1 GB CFI-compatible synchronous flash devices for non-volatile storage of FPGA configuration data, board information, test application data and user code space. These devices are part of the shared bus that connects to the flash memory, FPGA and MAX® V CPLD EPM2210 System Controller.

Table 34.  Memory Map of the first 1G flash (x16)
Block Description Size (KB) Address Range
Board Test System scratch 512 0x0750.0000 - 0x0757.FFFF
User software 14336 0x0670.0000 - 0x074F.FFFF
Factory software 8192 0x05F0.0000 - 0x06FF.FFFF
Zips (html, web content) 8192 0x0570.0000 - 0x05EF.FFFF
User hardware1 44032 0x02C0.0000 - 0x056F.FFFF
Factory hardware 44032 0x0010.0000 - 0x02BF.FFFF
PFL option bits 256 0x000C.0000 - 0x000F.FFFF
Board information 256 0x0008.0000 - 0x000B.FFFF
Ethernet option bits 256 0x0004.0000 - 0x0007.FFFF
User design reset vector 256 0x0000.0000 - 0x0003.FFFF
Table 35.  Memory Map of the second 1G flash (x16)
Block Description Size (KB) Address Range
User hardware2 44032 0x0010.0000 - 0x02BF.FFFF
PFL option bits 256 0x000C.0000 - 0x000F.FFFF
Reserved 256 0x0008.0000 - 0x000B.FFFF
Reserved 256 0x0004.0000 - 0x0007.FFFF
Reserved 256 0x0000.0000 - 0x0003.FFFF
Table 36.  Flash Memory Pin Assignments
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Description
F6 FLASH_ADVN BE28 1.8V Address Valid
B4 FLASH_CEN1 BJ31 1.8V Chip enable
E6 FLASH_CLK BF31 1.8V Clock
F8 FLASH_OEN BJ30 1.8V Output enable
F7 FLASH_RDYBSYN1 BJ28 1.8V Ready
D4 FLASH_RESETN BG30 1.8V Reset
G8 FLASH_WEN BH28 1.8V Write Enable
C6 FLASH_WPN – 1.8V Write protect
A1 FLASH_ADDR1 AU28 1.8V

Address bus
B1 FLASH_ADDR2 AU29 1.8V

Address bus
C1 FLASH_ADDR3 AW29 1.8V

Address bus
D1 FLASH_ADDR4 AY29 1.8V

Address bus
D2 FLASH_ADDR5 BB28 1.8V

Address bus
A2 FLASH_ADDR6 BA29 1.8V

Address bus
C2 FLASH_ADDR7 AV28 1.8V

Address bus
A3 FLASH_ADDR8 AW28 1.8V

Address bus
B3 FLASH_ADDR9 AV30 1.8V

Address bus
C3 FLASH_ADDR10 AU30 1.8V

Address bus
D3 FLASH_ADDR11 AT30 1.8V

Address bus
C4 FLASH_ADDR12 AT29 1.8V

Address bus
A5 FLASH_ADDR13 BA30 1.8V

Address bus
B5 FLASH_ADDR14 BA31 1.8V

Address bus
C5 FLASH_ADDR15 BB29 1.8V

Address bus
D7 FLASH_ADDR16 BB30 1.8V

Address bus
D8 FLASH_ADDR17 BC32 1.8V

Address bus
A7 FLASH_ADDR18 BC31 1.8V

Address bus
B7 FLASH_ADDR19 BB32 1.8V

Address bus
C7 FLASH_ADDR20 BA32 1.8V

Address bus
C8 FLASH_ADDR21 AY32 1.8V

Address bus
A8 FLASH_ADDR22 BD30 1.8V

Address bus
G1 FLASH_ADDR23 BC30 1.8V

Address bus
H8 FLASH_ADDR24 BG28 1.8V

Address bus
B6 FLASH_ADDR25 BG29 1.8V

Address bus
B8 FLASH_ADDR26 BH30 1.8V

Address bus
F2 FLASH_DATA0 BD36 1.8V

Data bus
E2 FLASH_DATA1 BE36 1.8V

Data bus
G3 FLASH_DATA2 BC35 1.8V

Data bus
E4 FLASH_DATA3 BC36 1.8V

Data bus
E5 FLASH_DATA4 BB34 1.8V

Data bus
G5 FLASH_DATA5 BB33 1.8V

Data bus
G6 FLASH_DATA6 BD35 1.8V

Data bus
H7 FLASH_DATA7 BD34 1.8V

Data bus
E1 FLASH_DATA8 BC33 1.8V

Data bus
E3 FLASH_DATA9 BD33 1.8V

Data bus
F3 FLASH_DATA10 BF35 1.8V

Data bus
F4 FLASH_DATA11 BF36 1.8V

Data bus
F5 FLASH_DATA12 BF34 1.8V

Data bus
H5 FLASH_DATA13 BG34 1.8V

Data bus
G7 FLASH_DATA14 BJ34 1.8V

Data bus
E7 FLASH_DATA15 BJ33 1.8V

Data bus
Level Two Title