Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

3.2. Default Switch and Jumper Settings

This topic shows you how to restore the default factory settings and explains their functions.

Figure 3. Default Switch Settings

1. Set DIP switch bank (SW2) to match the following table

Table 3.  SW2 DIP PCIe Switch Default Settings (Board Bottom)
Switch Board Label Function Default Position
1 x1 ON for PCIe x1 OFF
2 x4 ON for PCIe x4 OFF
3 x8 ON for PCIe x8 OFF
4 x16 ON for PCIe x16 ON

2. If all of the resistors are open, the FMC VCCIO value is 1.2 V. To change that value, add resistors as shown in the following table.

Table 4.  Default Resistor Settings for the FPGA Mezzanine (FMC) Ports (Board Bottom)
Board Reference Board Label Description
R460 1.35V 1.35V FMC VCCIO select
R464 1.5V 1.5V FMC VCCIO select
R468 1.8V 1.8V FMC VCCIO select
Note: A 0 Ohm resistor is installed by default

3. Set DIP switch bank (SW6) to match the following table.

Table 5.  SW6 JTAG Bypass DIP Switch Default Settings (Board Bottom)
Switch Board Label Function Default Position
1 Intel® Stratix® 10

OFF to enable the Intel® Stratix® 10 in the JTAG chain.

ON to bypass the Intel® Stratix® 10 in the JTAG chain.

OFF
2 MAX® V

OFF to enable the MAX® V in the JTAG chain.

ON to bypass the MAX® V in the JTAG chain.

OFF
3 FMC

OFF to enable the FMC Connector in the JTAG chain.

ON to bypass the FMC connector in the JTAG chain.

 ON

4. SW1 DIP Switch Default Settings (Board TOP)

Table 6.  SW1 DIP Switch Default Settings (Board TOP)
Switch Board Label Function
1 MSEL2

MSEL [2], MSEL [1] = [0,0] QSPI AS Fast Mode

MSEL [2], MSEL [1] = [0,1] QSPI AS Normal Mode

MSEL [2], MSEL [1] = [1,0] AVST x16 Mode (Default)

MSEL [2], MSEL [1] = [1,1] JTAG Only Mode

MSEL [0] is tied to Vcc
2 MSEL1

5. Set DIP switch bank (SW6) to match the following table.

Table 7.  SW3 DIP Switch Default Settings (Board Bottom)
Switch Board Label Function Default Position
1 CLK0_OEn

ON to enable the Si5341A clock device

OFF to disable the Si5341A clock device

ON
2 CLK0_RSTn

ON to hold the Si5341A clock device in reset

OFF to allow the Si5341A clock device to function normally

OFF
3 FACTORY_LOAD

ON to load factory image from flash

OFF to load user hardware1 from flash

 ON
Table 8.  SW4 DIP Switch Default Settings (Board Bottom)
Switch Board Label Function Default Position
1 RZQ_B2M

ON for setting RZQ resistor of Bank 2M to 99.17 Ohm

OFF for setting RZQ resistor of Bank 2M to 240 Ohm

 OFF
2 SI516_FS

ON for setting the SDI REFCLK frequency to 148.35 MHz

OFF for setting the SDI REFCLK frequency to 148.5 MHz

OFF
Table 9.  SW8 DIP Switch Default Settings (Board Bottom)
Switch Board Label Function Default Position
1 I2C_SDA Connects VRM I2C to MAX® V I2C chain ON
2 I2C_SCL Connects VRM I2C to MAX® V I2C chain ON
3 FPGA_PWRGD Connects LT2987 Power Good to MAX® V OFF
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