Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.6.4. FMC

The Intel® Stratix® 10 GX FPGA development board includes a high pin count (HPC) FPGA mezzanine card (FMC) connector that functions with a quadrature amplitude modulation (QAM) digital-to-analog converter (DAC) FMC module or daughtercard. This pin-out satisfies a QAM DAC that requires 58 low-voltage differential signaling (LVDS) data output pairs, one LVDS input clock pair and three low-voltage LVDS control pairs from the FPGA device. These pins also have the option to be used as single-ended I/O pins. The VCCIO supply for the FMC banks in the low pin count (LPC) and HPC provide a variable voltage of 1.2V, 1.35V, 1.5V and 1.8V (default).

Table 19.  FMC Connector Pin Assignments
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
D1 FMCA_C2M_PG – –
H5 FMCA_CLK_M2C_N0 AT17 Adjustable
G3 FMCA_CLK_M2C_N1 AR19 Adjustable
H4 FMCA_CLK_M2C_P0 AU17 Adjustable
G2 FMCA_CLK_M2C_P1 AT19 Adjustable
C3 FMCA_DP_C2M_N0 BJ5 1.4V PCML
A23 FMCA_DP_C2M_N1 BF6 1.4V PCML
A27 FMCA_DP_C2M_N2 BG4 1.4V PCML
A31 FMCA_DP_C2M_N3 BE4 1.4V PCML
A35 FMCA_DP_C2M_N4 BF2 1.4V PCML
A39 FMCA_DP_C2M_N5 BC4 1.4V PCML
B37 FMCA_DP_C2M_N6 BD2 1.4V PCML
B33 FMCA_DP_C2M_N7 BA4 1.4V PCML
B29 FMCA_DP_C2M_N8 BB2 1.4V PCML
B25 FMCA_DP_C2M_N9 AW4 1.4V PCML
K23 FMCA_DP_C2M_N10 AY2 1.4V PCML
K26 FMCA_DP_C2M_N11 AU4 1.4V PCML
K29 FMCA_DP_C2M_N12 AV2 1.4V PCML
K32 FMCA_DP_C2M_N13 AR4 1.4V PCML
K35 FMCA_DP_C2M_N14 AT2 1.4V PCML
K38 FMCA_DP_C2M_N15 AP2 1.4V PCML
C2 FMCA_DP_C2M_P0 BJ4 1.4V PCML
A22 FMCA_DP_C2M_P1 BF5 1.4V PCML
A26 FMCA_DP_C2M_P2 BG3 1.4V PCML
A30 FMCA_DP_C2M_P3 BE3 1.4V PCML
A34 FMCA_DP_C2M_P4 BF1 1.4V PCML
A38 FMCA_DP_C2M_P5 BC3 1.4V PCML
B36 FMCA_DP_C2M_P6 BD1 1.4V PCML
B32 FMCA_DP_C2M_P7 BA3 1.4V PCML
B28 FMCA_DP_C2M_P8 BB1 1.4V PCML
B24 FMCA_DP_C2M_P9 AW3 1.4V PCML
K22 FMCA_DP_C2M_P10 AY1 1.4V PCML
K25 FMCA_DP_C2M_P11 AU3 1.4V PCML
K28 FMCA_DP_C2M_P12 AV1 1.4V PCML
K31 FMCA_DP_C2M_P13 AR3 1.4V PCML
K34 FMCA_DP_C2M_P14 AT1 1.4V PCML
K37 FMCA_DP_C2M_P15 AP1 1.4V PCML
C7 FMCA_DP_M2C_N0 BH10 1.4V PCML
A3 FMCA_DP_M2C_N1 BJ8 1.4V PCML
A7 FMCA_DP_M2C_N2 BG8 1.4V PCML
A11 FMCA_DP_M2C_N3 BE8 1.4V PCML
A15 FMCA_DP_M2C_N4 BC8 1.4V PCML
A19 FMCA_DP_M2C_N5 BD6 1.4V PCML
B17 FMCA_DP_M2C_N6 BA8 1.4V PCML
B13 FMCA_DP_M2C_N7 BB6 1.4V PCML
B9 FMCA_DP_M2C_N8 AW8 1.4V PCML
B5 FMCA_DP_M2C_N9 AY6 1.4V PCML
K5 FMCA_DP_M2C_N10 AU8 1.4V PCML
K8 FMCA_DP_M2C_N11 AV6 1.4V PCML
K11 FMCA_DP_M2C_N12 AR8 1.4V PCML
K14 FMCA_DP_M2C_N13 AT6 1.4V PCML
K17 FMCA_DP_M2C_N14 AP6 1.4V PCML
K20 FMCA_DP_M2C_N15 AN8 1.4V PCML
C6 FMCA_DP_M2C_P0 BH9 1.4V PCML
A2 FMCA_DP_M2C_P1 BJ7 1.4V PCML
A6 FMCA_DP_M2C_P2 BG7 1.4V PCML
A10 FMCA_DP_M2C_P3 BE7 1.4V PCML
A14 FMCA_DP_M2C_P4 BC7 1.4V PCML
A18 FMCA_DP_M2C_P5 BD5 1.4V PCML
B16 FMCA_DP_M2C_P6 BA7 1.4V PCML
B12 FMCA_DP_M2C_P7 BB5 1.4V PCML
B8 FMCA_DP_M2C_P8 AW7 1.4V PCML
B4 FMCA_DP_M2C_P9 AY5 1.4V PCML
K4 FMCA_DP_M2C_P10 AU7 1.4V PCML
K7 FMCA_DP_M2C_P11 AV5 1.4V PCML
K10 FMCA_DP_M2C_P12 AR7 1.4V PCML
K13 FMCA_DP_M2C_P13 AT5 1.4V PCML
K16 FMCA_DP_M2C_P14 AP5 1.4V PCML
K19 FMCA_DP_M2C_P15 AN7 1.4V PCML
C34 FMCA_GA0 BJ20 Adjustable
D35 FMCA_GA1 BJ19 Adjustable
D5 FMCA_GBTCLK_M2C_N0 AP10 LVDS
B21 FMCA_GBTCLK_M2C_N1 AM10 LVDS
D4 FMCA_GBTCLK_M2C_P0 AP9 LVDS
B20 FMCA_GBTCLK_M2C_P1 AM9 LVDS
D34 FMCA_JTAG_RST – –
D29 FMCA_JTAG_TCK – –
D30 FMCA_JTAG_TDI – –
D31 FMCA_JTAG_TDO – –
D33 FMCA_JTAG_TMS – –
G7 FMCA_LA_RX_CLK_N0 AV10 LVDS
D9 FMCA_LA_RX_CLK_N1 BE21 LVDS
G6 FMCA_LA_RX_CLK_P0 AW10 LVDS
D8 FMCA_LA_RX_CLK_P1 BF21 LVDS
G10 FMCA_LA_RX_N0 AN18 LVDS
C11 FMCA_LA_RX_N1 AR21 LVDS
G13 FMCA_LA_RX_N2 AR18 LVDS
C15 FMCA_LA_RX_N3 AP20 LVDS
G16 FMCA_LA_RX_N4 AP16 LVDS
C19 FMCA_LA_RX_N5 BA19 LVDS
G19 FMCA_LA_RX_N6 AR16 LVDS
C23 FMCA_LA_RX_N7 BF19 LVDS
G22 FMCA_LA_RX_N8 AT16 LVDS
G25 FMCA_LA_RX_N9 AT14 LVDS
G28 FMCA_LA_RX_N10 AU14 LVDS
C27 FMCA_LA_RX_N11 BJ18 LVDS
G31 FMCA_LA_RX_N12 AU13 LVDS
G34 FMCA_LA_RX_N13 AY13 LVDS
G37 FMCA_LA_RX_N14 BE11 LVDS
G9 FMCA_LA_RX_P0 AN17 LVDS
C10 FMCA_LA_RX_P1 AT21 LVDS
G12 FMCA_LA_RX_P2 AP18 LVDS
C14 FMCA_LA_RX_P3 AN20 LVDS
G15 FMCA_LA_RX_P4 AP15 LVDS
C18 FMCA_LA_RX_P5 BB19 LVDS
G18 FMCA_LA_RX_P6 AR17 LVDS
C22 FMCA_LA_RX_P7 BE19 LVDS
G21 FMCA_LA_RX_P8 AT15 LVDS
G24 FMCA_LA_RX_P9 AR14 LVDS
G27 FMCA_LA_RX_P10 AU15 LVDS
C26 FMCA_LA_RX_P11 BH18 LVDS
G30 FMCA_LA_RX_P12 AV13 LVDS
G33 FMCA_LA_RX_P13 AW13 LVDS
G36 FMCA_LA_RX_P14 BE12 LVDS
H8 FMCA_LA_TX_N0 AP14 LVDS
H11 FMCA_LA_TX_N1 AU12 LVDS
D12 FMCA_LA_TX_N2 AU20 LVDS
H14 FMCA_LA_TX_N3 AV12 LVDS
D15 FMCA_LA_TX_N4 AW20 LVDS
H17 FMCA_LA_TX_N5 AW11 LVDS
D18 FMCA_LA_TX_N6 BB18 LVDS
H20 FMCA_LA_TX_N7 AY12 LVDS
D21 FMCA_LA_TX_N8 BD18 LVDS
H23 FMCA_LA_TX_N9 BA11 LVDS
H26 FMCA_LA_TX_N10 BB12 LVDS
D24 FMCA_LA_TX_N11 BF17 LVDS
H29 FMCA_LA_TX_N12 BB10 LVDS
D27 FMCA_LA_TX_N13 BH17 LVDS
H32 FMCA_LA_TX_N14 BC11 LVDS
H35 FMCA_LA_TX_N15 BD10 LVDS
H38 FMCA_LA_TX_N16 BF10 LVDS
H7 FMCA_LA_TX_P0 AP13 LVDS
H10 FMCA_LA_TX_P1 AT12 LVDS
D11 FMCA_LA_TX_P2 AT20 LVDS
H13 FMCA_LA_TX_P3 AV11 LVDS
D14 FMCA_LA_TX_P4 AW19 LVDS
H16 FMCA_LA_TX_P5 AY11 LVDS
D17 FMCA_LA_TX_P6 BC18 LVDS
H19 FMCA_LA_TX_P7 BA12 LVDS
D20 FMCA_LA_TX_P8 BE18 LVDS
H22 FMCA_LA_TX_P9 BA10 LVDS
H25 FMCA_LA_TX_P10 BC12 LVDS
D23 FMCA_LA_TX_P11 BE17 LVDS
H28 FMCA_LA_TX_P12 BC10 LVDS
D26 FMCA_LA_TX_P13 BG17 LVDS
H31 FMCA_LA_TX_P14 BD11 LVDS
H34 FMCA_LA_TX_P15 BE10 LVDS
H37 FMCA_LA_TX_P16 BF11 LVDS
F1 FMCA_M2C_PG – –
H2 FMCA_PRSNTN B22 1.8V
C30 FMCA_SCL BH21 3.3V
C31 FMCA_SDA BH20 3.3V
J39 VIO_B_M2C – –
K40 VIO_B_M2C – –
K1 VREF_B_M2C – –
H1 VREF_FMC – –
Level Two Title