Visible to Intel only — GUID: sam1403477493289
Ixiasoft
1. Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
2. Embedded Memory Blocks in Stratix V Devices
3. Variable Precision DSP Blocks in Stratix V Devices
4. Clock Networks and PLLs in Stratix V Devices
5. I/O Features in Stratix V Devices
6. High-Speed Differential I/O Interfaces and DPA in Stratix® V Devices
7. External Memory Interfaces in Stratix V Devices
8. Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
9. SEU Mitigation for Stratix V Devices
10. JTAG Boundary-Scan Testing in Stratix V Devices
11. Power Management in Stratix V Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Stratix V Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Memory Blocks Asynchronous Clear
2.11. Memory Blocks Error Correction Code Support
2.12. Embedded Memory Blocks in Stratix V Devices Revision History
4.2.1. PLL Physical Counters in Stratix V Devices
4.2.2. PLL Locations in Stratix® V Devices
4.2.3. PLL Migration Guidelines
4.2.4. Fractional PLL Architecture
4.2.5. PLL Cascading
4.2.6. PLL External Clock I/O Pins
4.2.7. PLL Control Signals
4.2.8. Clock Feedback Modes
4.2.9. Clock Multiplication and Division
4.2.10. Programmable Phase Shift
4.2.11. Programmable Duty Cycle
4.2.12. Clock Switchover
4.2.13. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O Standards Support in Stratix V Devices
5.2. I/O Design Guidelines for Stratix V Devices
5.3. I/O Banks in Stratix® V Devices
5.4. I/O Banks Groups in Stratix V Devices
5.5. I/O Element Structure in Stratix V Devices
5.6. Programmable IOE Features in Stratix® V Devices
5.7. On-Chip I/O Termination in Stratix® V Devices
5.8. I/O Termination Schemes for Stratix® V Devices
5.9. I/O Features in Stratix V Devices Revision History
5.6.1. Programmable Current Strength
5.6.2. Programmable Output Slew Rate Control
5.6.3. Programmable IOE Delay
5.6.4. Programmable Output Buffer Delay
5.6.5. Programmable Pre-Emphasis
5.6.6. Programmable Differential Output Voltage
5.6.7. Open-Drain Output
5.6.8. Bus-Hold Circuitry
5.6.9. Pull-up Resistor
5.7.1. RS OCT without Calibration in Stratix® V Devices
5.7.2. RS OCT with Calibration in Stratix® V Devices
5.7.3. RT OCT with Calibration in Stratix® V Devices
5.7.4. Dynamic OCT in Stratix® V Devices
5.7.5. LVDS Input RD OCT in Stratix V Devices
5.7.6. OCT Calibration Block in Stratix V Devices
5.7.7. OCT Calibration in Power-Up Mode
5.7.8. OCT Calibration in User Mode
6.1. Dedicated High-Speed Circuitries in Stratix® V Devices
6.2. High-Speed I/O Design Guidelines for Stratix® V Devices
6.3. Differential Transmitter in Stratix V Devices
6.4. Differential Receiver in Stratix V Devices
6.5. Source-Synchronous Timing Budget
6.6. High-Speed Differential I/O Interfaces and DPA in Stratix® V Devices Revision History
7.3.1. UniPHY IP
7.3.2. External Memory Interface Datapath
7.3.3. DQS Phase-Shift Circuitry
7.3.4. Phase Offset Control
7.3.5. PHY Clock (PHYCLK) Networks
7.3.6. DQS Logic Block
7.3.7. Leveling Circuitry
7.3.8. Dynamic OCT Control
7.3.9. IOE Registers
7.3.10. Delay Chains
7.3.11. I/O and DQS Configuration Blocks
8.1. Enhanced Configuration and Configuration via Protocol
8.2. MSEL Pin Settings
8.3. Configuration Sequence
8.4. Configuration Timing Waveforms
8.5. Device Configuration Pins
8.6. Fast Passive Parallel Configuration
8.7. Active Serial Configuration
8.8. Using EPCS and EPCQ Devices
8.9. Passive Serial Configuration
8.10. JTAG Configuration
8.11. Configuration Data Compression
8.12. Remote System Upgrades
8.13. Design Security
8.14. Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Revision History
10.1. BST Operation Control
10.2. I/O Voltage for JTAG Operation
10.3. Performing BST
10.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
10.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
10.6. IEEE Std. 1149.1 Boundary-Scan Register
10.7. IEEE Std. 1149.6 Boundary-Scan Register
10.8. JTAG Boundary-Scan Testing inStratix V Devices Revision History
Visible to Intel only — GUID: sam1403477493289
Ixiasoft
4.2.12.4. Guidelines
When implementing clock switchover in Stratix® V PLLs, use the following guidelines:
- Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of each other. Failing to meet this requirement causes the clkbad[0] and clkbad[1] signals to not function properly.
- When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2×). However, differences in frequency, phase, or both, of the two clock sources will likely cause the PLL to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships between the input and output clocks.
- Both inclk0 and inclk1 must be running when the extswitch signal goes high to initiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
- Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a high-bandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clock to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL also increases lock time.
- After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new clock. The time it takes for the PLL to relock depends on the PLL configuration.
- The phase relationship between the input clock to the PLL and the output clock from the PLL is important in your design. Assert areset for at least 10 ns after performing a clock switchover. Wait for the locked signal to go high and be stable before re-enabling the output clocks from the PLL.
- The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO locks on to the backup clock, as shown in the following figure.
Figure 87. VCO Switchover Operating Frequency