AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

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ID 683640
Date 10/14/2019
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Document Table of Contents
Document Table of Contents x
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores x
1.1. Fractional PLL Reconfiguration in 28-nm Devices 1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software 1.3. Design Considerations 1.4. Using the Design Examples 1.5. Tutorial Walkthrough 1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1.1. Fractional PLL Reconfiguration in 28-nm Devices x
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software x
1.1.1.1. Connectivity between Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.2. Connecting Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core 1.1.1.4. Registers and Counters Settings 1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface 1.1.1.6. .mif Streaming Reconfiguration
1.1.1.4. Registers and Counters Settings x
1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings 1.1.1.4.2. Counter Address and Bit Setting During Read Operation 1.1.1.4.3. Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting
1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface x
1.1.1.5.1. Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface
1.1.1.6. .mif Streaming Reconfiguration x
1.1.1.6.1. Stitching Two .mif Files Generated by the Intel® Quartus® Prime Software 1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core 1.1.1.6.3. .mif File Format 1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes
1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software x
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core 1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core x
1.2.1.1. Waveform Example for Dynamic Phase Shift with Altera PLL IP Core 1.2.1.2. Dynamic Phase Shift Signals in Altera PLL IP Core 1.2.1.3. Logical Counter Bit Setting
1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core x
1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core
1.4. Using the Design Examples x
1.4.1. Software Requirement 1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters 1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift 1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow 1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core 1.4.6. Design Example 5: .mif Streaming Reconfiguration
1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow x
1.4.4.1. Qsys System and Components 1.4.4.2. Main Menu Commands in Qsys 1.4.4.3. Submenu Commands in Qsys
1.5. Tutorial Walkthrough x
1.5.1. Creating a New Intel® Quartus® Prime Project 1.5.2. Creating the Qsys System 1.5.3. Creating the Top-Level Design File 1.5.4. Incorporating the Nios II SBT for Eclipse 1.5.5. Verifying Design on Hardware
1.5.4. Incorporating the Nios II SBT for Eclipse x
1.5.4.1. Adding Test Code to the Nios II SBT for Eclipse 1.5.4.2. Setting Up the Nios II Project Settings
1.5.5. Verifying Design on Hardware x
1.5.5.1. Compiling the Project 1.5.5.2. Downloading the Object File 1.5.5.3. Verifying Design with the Nios II SBT for Eclipse
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface

You can dynamically reconfigure fPLLs with the Avalon®-MM interface. To perform dynamic reconfiguration, follow these steps:

  1. Through an Avalon write operation, write to the mode register a value of 0 or 1 at the startup of the Altera PLL Reconfig IP core. The mode register determines whether the Altera PLL Reconfig IP core operates in waitrequest or polling mode.
  2. Specify the element and its new value through an Avalon write operation.
    For more information about the address for each reconfigurable element, refer to Fractional PLL Dynamic Reconfiguration Registers and Settings, and Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting tables.
  3. Repeat Step 2 for all the reconfigurable elements (N, M, C counters, MFRAC value, and others) that you want to change.
  4. Through an Avalon write operation, write either 0 or 1 to the start register. Writing to the start register triggers the dynamic reconfiguration, the dynamic phase shift, or both:
    • If you set the mode register to 0 (waitrequest mode) in Step 1, the Altera PLL Reconfig IP core asserts the mgmt_waitrequest signal until after the reconfiguration. You can only perform another Avalon read or write operation after the Altera PLL Reconfig IP core deasserts the mgmt_waitrequest signal.
    • If you set the mode register to 1 (polling mode) in Step 1, the Altera PLL Reconfig IP core writes 0 (busy) to the status register. You can poll bit 0 of the status register periodically by performing Avalon read operations to ensure that the reconfiguration is complete. The Altera PLL Reconfig IP core ignores any new reconfiguration instructions (Avalon write operations) until a value of 1 has been read from the status register.
    Lock the fractional PLL to the reference clock before you perform the dynamic reconfiguration or the dynamic phase shifting.

Section Content
Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface

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