AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

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ID 683640
Date 10/14/2019
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores x
1.1. Fractional PLL Reconfiguration in 28-nm Devices 1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software 1.3. Design Considerations 1.4. Using the Design Examples 1.5. Tutorial Walkthrough 1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1.1. Fractional PLL Reconfiguration in 28-nm Devices x
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software x
1.1.1.1. Connectivity between Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.2. Connecting Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core 1.1.1.4. Registers and Counters Settings 1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface 1.1.1.6. .mif Streaming Reconfiguration
1.1.1.4. Registers and Counters Settings x
1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings 1.1.1.4.2. Counter Address and Bit Setting During Read Operation 1.1.1.4.3. Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting
1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface x
1.1.1.5.1. Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface
1.1.1.6. .mif Streaming Reconfiguration x
1.1.1.6.1. Stitching Two .mif Files Generated by the Intel® Quartus® Prime Software 1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core 1.1.1.6.3. .mif File Format 1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes
1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software x
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core 1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core x
1.2.1.1. Waveform Example for Dynamic Phase Shift with Altera PLL IP Core 1.2.1.2. Dynamic Phase Shift Signals in Altera PLL IP Core 1.2.1.3. Logical Counter Bit Setting
1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core x
1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core
1.4. Using the Design Examples x
1.4.1. Software Requirement 1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters 1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift 1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow 1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core 1.4.6. Design Example 5: .mif Streaming Reconfiguration
1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow x
1.4.4.1. Qsys System and Components 1.4.4.2. Main Menu Commands in Qsys 1.4.4.3. Submenu Commands in Qsys
1.5. Tutorial Walkthrough x
1.5.1. Creating a New Intel® Quartus® Prime Project 1.5.2. Creating the Qsys System 1.5.3. Creating the Top-Level Design File 1.5.4. Incorporating the Nios II SBT for Eclipse 1.5.5. Verifying Design on Hardware
1.5.4. Incorporating the Nios II SBT for Eclipse x
1.5.4.1. Adding Test Code to the Nios II SBT for Eclipse 1.5.4.2. Setting Up the Nios II Project Settings
1.5.5. Verifying Design on Hardware x
1.5.5.1. Compiling the Project 1.5.5.2. Downloading the Object File 1.5.5.3. Verifying Design with the Nios II SBT for Eclipse
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

1.5.3. Creating the Top-Level Design File

You can consider the Qsys system as a component in your design. The Qsys system can be the only component or one of many components. Hence, when your Qsys system is complete, you must add the system to your top-level design.

The top-level design can be in your preferred HDL language or a .bdf schematic design.

In this walkthrough, the top-level design is a simple wrapper file around the Qsys system with no additional components. The top-level design defines only the pin naming convention and port connection.

Figure 8. Qsys Top-Level Block Diagram

To create a top-level design for your Qsys system with a .bdf schematic, follow these steps:

  1. In the Intel® Quartus® Prime software, on the File menu, click New.
  2. Select the Block Diagram/Schematic file and click OK.
    A blank .bdf, Block1.bdf, opens.
  3. On the File menu, click Save as. In the Save As dialog box, click Save.
    The Intel® Quartus® Prime software sets the .bdf file name to your project name automatically.
  4. Right-click in the blank.bdf, point to Insert and click Symbol to open the Symbol dialog box.
  5. Expand Project, under Libraries select system, click OK.
  6. Add system.qip to the project.
  7. Connect the reconfig_to_pll[63:0] bus on the Altera PLL Reconfig instance to the reconfig_to_pll[63:0] bus on the Altera PLL instance.
  8. Connect the reconfig_from_pll[63:0] bus on the Altera PLL instance to the reconfig_from_pll[63:0] bus on the Altera PLL Reconfig instance.
  9. Position the Qsys system component and click Generate pins for Symbol Ports to automatically add pins and nets to the schematic symbol.
  10. Rename the existing pins to the modified pin names as follows:
    Existing Pin Name Modified Pin Name
    clk_clk inclk
    reset_reset_n reset_n
    pll_0_reset_reset areset
    pll_0_locked_export locked
    pll_0_outclk0_clk co_ouput
    pll_0_outclk1_clk c1_ouptut
    pll_0_outclk10_clk c10_ouptut
    pll_0_outclk5_clk c5_output
  11. Connect the pll_refclk_clk port to the inclk pin.
  12. On the File menu, click Save.
  13. On the Project menu, click Set as Top-Level Entity.
  14. Assign the I/O standard and pin locations for all pins in your design.
  15. Add the timing constraint to the .sdc file to constrain the input clock of your design.
  16. Compile your design.
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