AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

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ID 683640
Date 10/14/2019
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores x
1.1. Fractional PLL Reconfiguration in 28-nm Devices 1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software 1.3. Design Considerations 1.4. Using the Design Examples 1.5. Tutorial Walkthrough 1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1.1. Fractional PLL Reconfiguration in 28-nm Devices x
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software x
1.1.1.1. Connectivity between Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.2. Connecting Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core 1.1.1.4. Registers and Counters Settings 1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface 1.1.1.6. .mif Streaming Reconfiguration
1.1.1.4. Registers and Counters Settings x
1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings 1.1.1.4.2. Counter Address and Bit Setting During Read Operation 1.1.1.4.3. Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting
1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface x
1.1.1.5.1. Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface
1.1.1.6. .mif Streaming Reconfiguration x
1.1.1.6.1. Stitching Two .mif Files Generated by the Intel® Quartus® Prime Software 1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core 1.1.1.6.3. .mif File Format 1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes
1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software x
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core 1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core x
1.2.1.1. Waveform Example for Dynamic Phase Shift with Altera PLL IP Core 1.2.1.2. Dynamic Phase Shift Signals in Altera PLL IP Core 1.2.1.3. Logical Counter Bit Setting
1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core x
1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core
1.4. Using the Design Examples x
1.4.1. Software Requirement 1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters 1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift 1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow 1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core 1.4.6. Design Example 5: .mif Streaming Reconfiguration
1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow x
1.4.4.1. Qsys System and Components 1.4.4.2. Main Menu Commands in Qsys 1.4.4.3. Submenu Commands in Qsys
1.5. Tutorial Walkthrough x
1.5.1. Creating a New Intel® Quartus® Prime Project 1.5.2. Creating the Qsys System 1.5.3. Creating the Top-Level Design File 1.5.4. Incorporating the Nios II SBT for Eclipse 1.5.5. Verifying Design on Hardware
1.5.4. Incorporating the Nios II SBT for Eclipse x
1.5.4.1. Adding Test Code to the Nios II SBT for Eclipse 1.5.4.2. Setting Up the Nios II Project Settings
1.5.5. Verifying Design on Hardware x
1.5.5.1. Compiling the Project 1.5.5.2. Downloading the Object File 1.5.5.3. Verifying Design with the Nios II SBT for Eclipse
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes

Table 5.  .mif Streaming Reconfiguration Operation Codes
Operation Name Operation Code Description
Start of .mif (SOM) 111110 Indicates start of single PLL configuration
End of .mif (EOM) 111111 Indicates end of single PLL configuration

Each .mif streaming reconfiguration must be indicated with a SOM and EOM opcodes.

The remaining opcodes are the addresses for each of the registers in the Altera PLL Reconfig IP core.

You can save multiple PLL configurations in a .mif file if you mark the SOM or EOM opcodes appropriately. The .mif reader reads the settings from an M20K RAM block, which has default address width = 9 bits, data width = 32 bits (total words = 512). These sizes can change as parameters are passed to the top-level module. For .mif streaming reconfiguration, data width must be 32 bits to match the Altera PLL Reconfig IP core.

The M20K is initialized by MIF_FILE_NAME, also a top-level parameter. On the start of .mif streaming operation, the .mif reader checks the .mif base address in the M20K RAM block for a SOM opcode. The .mif reader continues to read the file until EOM opcode is reached.

You can generate a .mif file independently with a PLL .mif configuration file generated by the Altera PLL parameter editor. The generated .mif file stores the entire PLL profile.

You can also construct your own .mif files by stitching together existing .mif files or writing your own commands (following the .mif syntax). This allows what settings are stored in the M20K for future reconfiguration.

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