AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

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ID 683640
Date 10/14/2019
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Document Table of Contents
Document Table of Contents x
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores x
1.1. Fractional PLL Reconfiguration in 28-nm Devices 1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software 1.3. Design Considerations 1.4. Using the Design Examples 1.5. Tutorial Walkthrough 1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1.1. Fractional PLL Reconfiguration in 28-nm Devices x
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software x
1.1.1.1. Connectivity between Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.2. Connecting Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core 1.1.1.4. Registers and Counters Settings 1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface 1.1.1.6. .mif Streaming Reconfiguration
1.1.1.4. Registers and Counters Settings x
1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings 1.1.1.4.2. Counter Address and Bit Setting During Read Operation 1.1.1.4.3. Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting
1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface x
1.1.1.5.1. Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface
1.1.1.6. .mif Streaming Reconfiguration x
1.1.1.6.1. Stitching Two .mif Files Generated by the Intel® Quartus® Prime Software 1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core 1.1.1.6.3. .mif File Format 1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes
1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software x
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core 1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core x
1.2.1.1. Waveform Example for Dynamic Phase Shift with Altera PLL IP Core 1.2.1.2. Dynamic Phase Shift Signals in Altera PLL IP Core 1.2.1.3. Logical Counter Bit Setting
1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core x
1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core
1.4. Using the Design Examples x
1.4.1. Software Requirement 1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters 1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift 1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow 1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core 1.4.6. Design Example 5: .mif Streaming Reconfiguration
1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow x
1.4.4.1. Qsys System and Components 1.4.4.2. Main Menu Commands in Qsys 1.4.4.3. Submenu Commands in Qsys
1.5. Tutorial Walkthrough x
1.5.1. Creating a New Intel® Quartus® Prime Project 1.5.2. Creating the Qsys System 1.5.3. Creating the Top-Level Design File 1.5.4. Incorporating the Nios II SBT for Eclipse 1.5.5. Verifying Design on Hardware
1.5.4. Incorporating the Nios II SBT for Eclipse x
1.5.4.1. Adding Test Code to the Nios II SBT for Eclipse 1.5.4.2. Setting Up the Nios II Project Settings
1.5.5. Verifying Design on Hardware x
1.5.5.1. Compiling the Project 1.5.5.2. Downloading the Object File 1.5.5.3. Verifying Design with the Nios II SBT for Eclipse
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

1.3. Design Considerations

You must consider the following information when using fPLL reconfiguration:

  • Changing prescale and feedback counter settings (M, N, MFRAC), charge pump/loop filter settings affects the fractional PLL VCO frequency, which may require the fractional PLL to relock to the reference clock.
  • Changing the M counter phase shift setting changes the phase relationship of the output clocks with respect to the fractional PLL reference clock, which also requires the fractional PLL to relock. Although the exact effect of changing prescale and feedback counter settings (M, N) depends on the changes to the settings, any changes require relocking.
  • Adding phase shift using the M counter phase shift setting pulls in all the fractional PLL clock outputs with respect to the reference clock. This effectively adds a negative phase shift because the M counter is in the feedback path.
  • When making changes to the loop elements (M, N, MFRAC, M counter phase, Icp, R, C), Altera recommends disabling fractional PLL outputs to the logic array using the clkena signals available on the ALTCLKCTRL IP core. This recommendation eliminates the possibility of an over frequency condition affecting system logic while fractional PLL is regaining lock.
  • Changing the K counter values is only effective if the PLL is in fractional mode before reconfiguration.
  • Changing post-scale counters (C) and phase do not affect the fractional PLL lock status or VCO frequency. The resolution of phase shift is a function of VCO frequency, with the smallest incremental step equal to 1/8th of the VCO period.
  • Altera recommends resynchronizing the fractional PLL using the areset signal if the phase relationship between output clocks is important. Always assert the areset signal after each mgmt_reset operation or after each fPLL reconfiguration process, to reinitiate the fPLL locking process.
  • Fractional PLL reconfiguration interface supports a free running mgmt_clk signal, eliminating the need to precisely control the start and stop of mgmt_clk signal.
  • Changing the M or N counter values affect all the output clock frequencies.
  • C counters can also be reconfigured individually.
  • You can perform phase shifting even if C counter is set to 1 and bypass is enabled.
  • When the PLL has two clocks with 0 degree initial phase shift between the clocks, the Fitter synthesizes away the second clock automatically. To prevent the clocks from merging, Altera recommends manually performing location constraint for each of the PLL output counters which share the same frequency and phase shift.
  • Readback counter operation needs at least three scanclk cycle latency.
  • In waitrequest mode, the mgmt_waitrequest signal deasserts when PLL reconfiguration is complete. If the PLL loses lock after reconfiguration is complete, assert the mgmt_waitrequest signal again until the PLL locks. There may be a brief period after PLL reconfiguration is complete, but before the PLL has lost lock, when the mgmt_waitrequest signal is de-asserted. Altera recommends allowing sufficient time for the PLL to lock after PLL reconfiguration is complete before performing a new Avalon read or write operation.
  • In polling mode, the status register changes from 0 (busy) to 1 (ready) when PLL reconfiguration is complete. If the PLL loses lock after reconfiguration is complete, the status register is at 0 (busy) until the PLL locks. There may be a brief period after PLL reconfiguration is complete, but before the PLL has lost lock, when the status register is at 1 (ready). Altera recommends allowing sufficient time for the PLL to lock after PLL reconfiguration is complete before performing a new Avalon read or write operation.
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