AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

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ID 683640
Date 10/14/2019
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores x
1.1. Fractional PLL Reconfiguration in 28-nm Devices 1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software 1.3. Design Considerations 1.4. Using the Design Examples 1.5. Tutorial Walkthrough 1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1.1. Fractional PLL Reconfiguration in 28-nm Devices x
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software x
1.1.1.1. Connectivity between Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.2. Connecting Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core 1.1.1.4. Registers and Counters Settings 1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface 1.1.1.6. .mif Streaming Reconfiguration
1.1.1.4. Registers and Counters Settings x
1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings 1.1.1.4.2. Counter Address and Bit Setting During Read Operation 1.1.1.4.3. Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting
1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface x
1.1.1.5.1. Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface
1.1.1.6. .mif Streaming Reconfiguration x
1.1.1.6.1. Stitching Two .mif Files Generated by the Intel® Quartus® Prime Software 1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core 1.1.1.6.3. .mif File Format 1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes
1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software x
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core 1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core x
1.2.1.1. Waveform Example for Dynamic Phase Shift with Altera PLL IP Core 1.2.1.2. Dynamic Phase Shift Signals in Altera PLL IP Core 1.2.1.3. Logical Counter Bit Setting
1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core x
1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core
1.4. Using the Design Examples x
1.4.1. Software Requirement 1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters 1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift 1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow 1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core 1.4.6. Design Example 5: .mif Streaming Reconfiguration
1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow x
1.4.4.1. Qsys System and Components 1.4.4.2. Main Menu Commands in Qsys 1.4.4.3. Submenu Commands in Qsys
1.5. Tutorial Walkthrough x
1.5.1. Creating a New Intel® Quartus® Prime Project 1.5.2. Creating the Qsys System 1.5.3. Creating the Top-Level Design File 1.5.4. Incorporating the Nios II SBT for Eclipse 1.5.5. Verifying Design on Hardware
1.5.4. Incorporating the Nios II SBT for Eclipse x
1.5.4.1. Adding Test Code to the Nios II SBT for Eclipse 1.5.4.2. Setting Up the Nios II Project Settings
1.5.5. Verifying Design on Hardware x
1.5.5.1. Compiling the Project 1.5.5.2. Downloading the Object File 1.5.5.3. Verifying Design with the Nios II SBT for Eclipse
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

1.5.2. Creating the Qsys System

To create a Qsys system, follow these steps:

  1. On the Tool menu, click Qsys.
  2. Add the Qsys components that your design requires.
    1. To create an Altera PLL instance, perform these steps:
      1. Expand PLL, select Altera PLL, and click Add.
      2. Set Reference Clock Frequency to 50.0 MHz.
      3. Select the number of output clock and set its output frequency and phase relationship.
      4. In the Settings tab, turn on the Enable dynamic reconfiguration of PLL option.
      5. Click Finish.
    2. To create an Altera PLL Reconfig instance, perform these steps:
      1. Expand PLL, select Altera PLL Reconfig, and click Add.
      2. Click Finish.
    3. Under Component Library > Memories and Memory Controllers > On-Chip, select On-Chip Memory (RAM or ROM), and then click Add.
      1. For Total Memory size, type 65536 bytes.
      2. Click Finish.
    4. Under Component Library, expand Embedded Processors, select Nios II Processor and click Add.
      1. Select Nios II/s.
      2. Set Reset Vector Offset to 0x00 and Exception Vector Offset to 0x20.
      3. Click Finish.
    5. Under Interface Protocols > Serial, select JTAG UART and click Add.
      1. Under Write FIFO and Read FIFO, for the Buffer depth (bytes) select 64, and for IRQ threshold type 8.
      2. For Prepare interactive windows, select INTERACTIVE_INPUT_OUTPUT to open the interactive display window during simulation.
      3. Click Finish.
    6. In the Project Setting tab, for Clock Crossing Adapter Type, select Auto.
  3. In the System Contents tab, make the appropriate bus connection and IRQ lines as shown in Qsys System and Components for Design Example 3 figure.
    If there are warnings about overlapping addresses, on the System menu, click Assign Base Addresses. If there are warnings about overlapping IRQ, on the System menu, click Assign Interrupt numbers.
  4. After setting up the connections, right-click the Nios II Processor and select Edit to open the Nios II Processor parameter editor. In the Core Nios II tab, for Reset vector memory and Exception vector memory, select onchip_memory2_0.s1, and click Finish.
  5. On the File menu, click Save.
  6. In the Generation tab, under Synthesis, turn on Create HDL design files for synthesis and Create block symbol file (.bsf).
  7. Click Generate.
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