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2.1. Installation and Licensing
2.2. Generating aCPRI Intel® FPGA IP
2.3. CPRI Intel® FPGA IP Generated Files
2.4. CPRI Intel® FPGA IP Parameters
2.5. Integrating the CPRI IP into your Design: Required External Blocks
2.6. Simulating Intel FPGA IP Cores
2.7. Running the CPRI IP Design Example
2.8. CPRI Design Example Clocks
2.9. About the Testbench
2.10. Compiling the Full Design and Programming the FPGA
2.5.1. Adding the Transceiver TX PLL IP Core
2.5.2. Adding the Reset Controller
2.5.3. Adding the Transceiver Reconfiguration Controller
2.5.4. Adding the Off-Chip Clean-Up PLL
2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks
2.5.6. CPRI IP Transceiver PLL Calibration
2.5.7. Reference and System PLL Clock for your IP Design
3.1. Interfaces Overview
3.2. CPRI Intel® FPGA IP Clocking Structure
3.3. CPRI Intel® FPGA IP Core Reset Requirements
3.4. Start-Up Sequence Following Reset
3.5. AUX Interface
3.6. Direct IQ Interface
3.7. Ctrl_AxC Interface
3.8. Direct Vendor Specific Access Interface
3.9. Real-Time Vendor Specific Interface
3.10. Direct HDLC Serial Interface
3.11. Direct L1 Control and Status Interface
3.12. L1 Debug Interface
3.13. Media Independent Interface (MII) to External Ethernet Block
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block
3.15. CPU Interface to CPRI Intel® FPGA IP Registers
3.16. Auto-Rate Negotiation
3.17. Extended Delay Measurement
3.18. Deterministic Latency and Delay Measurement and Calibration
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces
3.20. Testing Features
3.19.1. CPRI Link
3.19.2. Main Transceiver Clock and Reset Signals
3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface
3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface
3.19.5. RS-FEC Interface
3.19.6. Interface to the External Reset Controller
3.19.7. Interface to the External PLL
3.19.8. Transceiver Debug Interface
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3.18.3.2. Tx Path Delay
The Tx path delay is the cumulative delay from the arrival of the first bit of a 10 ms radio frame on the CPRI AUX interface (or other direct interface) to the start of transmission of this data on the CPRI link.
Figure 62. Tx Path Delay from AUX Interface to CPRI Link in CPRI Intel® FPGA IP Core
The Tx path delay from the AUX interface to the CPRI link is the sum of the following delays:
- Fixed delay from the AUX interface though the CPRI low-level transmitter to the Tx elastic buffer. This delay depends on the device family and the current CPRI line bit rate.
- Variable delay through the Tx elastic buffer, as well as the phase difference between the core clock cpri_clkout and the transceiver tx_clkout clock. The "Extended Delay Measurement" section shows how to calculate the delay in the CPRI Intel® FPGA IP Tx elastic buffer, which includes the phase difference delay.
- Variable Tx bitslip delay in CPRI RE slaves. Refer to "Tx Bitslip Delay."
- Fixed delay from the Tx elastic buffer to the transceiver. This delay depends on the device family and the CPRI line bit rate.
Note: In Intel® FPGA IP core variations that target an Stratix® 10 device, you must also add the delay through the Stratix 10 hard FIFOs in the Tx path. Refer to "Extended Delay Measurement for Stratix® 10 Hard FIFOs" section.
- Link delay through the transceiver.