CPRI Intel® FPGA IP User Guide

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ID 683595
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP 2. Getting Started with the CPRI Intel® FPGA IP 3. CPRI IP Functional Description 4. CPRI Intel® FPGA IP Signals 5. CPRI Intel® FPGA IP Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support 1.3. Intel® FPGA IP Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP 1.5. CPRI IP Release Information
1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI Intel® FPGA IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP x
2.1. Installation and Licensing 2.2. Generating aCPRI Intel® FPGA IP 2.3. CPRI Intel® FPGA IP Generated Files 2.4. CPRI Intel® FPGA IP Parameters 2.5. Integrating the CPRI IP into your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Running the CPRI IP Design Example 2.8. CPRI Design Example Clocks 2.9. About the Testbench 2.10. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating the CPRI IP into your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. CPRI IP Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
2.5.7. Reference and System PLL Clock for your IP Design x
2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.5.7.2. System PLL Connections for the Agilex 5 Variations 2.5.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP
2. Getting Started with the CPRI Intel® FPGA IP
3. CPRI IP Functional Description
4. CPRI Intel® FPGA IP Signals
5. CPRI Intel® FPGA IP Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

2.7. Running the CPRI IP Design Example

  1. In the Quartus® Prime software IP Catalog, select the CPRI Intel® FPGA IP and click Add.
  2. When prompted, you can specify any output file type (HDL). This setting is relevant only for synthesis and does not impact simulation of the demonstration testbench.
  3. In the CPRI parameter editor, set the following parameter values:
    Table 17.   CPRI Intel® FPGA IP Core Variation for Demonstration TestbenchThe testbench scripts require that you set these values in the CPRI parameter editor before you click Generate Example Design. The scripts generate the DUT but they require that you provide the parameter values.
    Parameter Value
    Line bit rate (Mbit/s) Any value the device family supports.
    Synchronization mode Host
    Enable Reed-Solomon Forward Error Correction (RSFEC) Turn Off
    Operation mode Any available mode
    Transmitter local clock division factor 1
    Number of receiver CDR reference clock(s) 1
    Receiver CDR reference clock frequency (MHz)

    253.44 if the Line bit rate is 8.11008 or 10.1376 or 12.16512 Gbps and the IP targets the Stratix® 10 device family

    368.64 if the Line bit rate is 24.33024 Gbps and the IP targets the Stratix® 10 device family

    253.44 if the Line bit rate is 8.11008 or 10.1376 Gbps and the IP targets the Arria® 10 device family

    253.44 if the Line bit rate is 8.11008 or 10.1376 Gbps and the IP targets a 28-nm device family

    253.44 if the Line bit rate is 8.11008 Gbps and the IP targets Arria® V GZ device family

    307.2 for all other cases

    Unused for E-tile, F-tile, and Intel Agilex 5 devices.
    Core clock source input Internal or External
    Recovered clock source PMA if the Line bit rate is 10.1376 Gbps and IP core targets the Stratix V device family; PCS otherwise. Unused for E-tile, F-tile, and Agilex 5 devices.
    PMA reference frequency (MHz)

    184.32 if the line bit rate is 10.1376 Gbps; 153.6 otherwise. Only for Agilex 5 devices.
    Receiver soft buffer depth (value shown is log2 of actual depth) 6
    Enable line bit rate auto-negotiation Turn on or off
    Enable line bit rate auto-negotiation down to 614.4 Mbps Not available
    Management (CSR) interface standard Avalon® memory-mapped
    Avalon-MM interface addressing type Word
    Auxiliary and direct interfaces write latency cycle(s) 0
    Enable auxiliary interface Turn on or Turn off
    Enable resyncronization of CPRI radio frame number to desired value Turn on or Turn off
    Enable all control word access via management interface Turn off
    Enable direct Z.130.0 alarm bits access interface Turn off
    Enable direct ctrl_axc access interface Turn on or Turn off
    Enable direct vendor specific access interface Turn on or Turn off
    Enable direct real-time vendor specific interface Turn on or Turn off
    Enable start-up sequence state machine Turn off
    Enable protocol version and C&M channel setting auto-negotiation Not available
    Enable direct IQ mapping interface Turn on or Turn off
    Enable HDLC serial interface Turn on or Turn off
    Ethernet PCS interface NONE, MII or GMII
    Ethernet PCS Bypass Turn on or Turn off
    Enable run time switch of GMII PCS Turn on or Turn off
    L2 Ethernet PCS Tx/Rx FIFO depth (value shown is log2 of actual depth) 8
    Enable L1 debug interfaces Turn off
    Enable Native PHY Debug Master Endpoint (NPDME), transceiver capability, control and status registers access Turn off
    Enable transceiver PMA serial forward loopback path Turn off
    Enable parallel forward loopback paths Turn off
    Enable parallel reversed loopback paths Turn off
    Enable single-trip delay calibration Not available
    Enable round-trip delay calibration Turn off
    Round-trip delay calibration FIFO depth Not available
    Language for top-level simulation file
    • Verilog
    • VHDL
    Enable Auto Rate Negotiation ED You must turn on if you have turned on parameter Enable line bit rate auto-negotiation and vice versa.
  4. In the CPRI parameter editor, click the Generate Example Design button and specify the desired location of the testbench.
  5. Change directory to <your_ip>/setup_scripts/<simulator_vendor> .
  6. For Agilex® 7 F-tile devices, perform these additional steps:
    1. Navigate to the <your_ip>/ip_components directory and perform these two commands: 
      quartus_ipgenerate --run_default_mode_op tb_top -c tb_top
      quartus_tlg tb_top
      Alternately, you may open the tb_top.qpf project in Quartus® Prime and perform the compilation until support logic generation stage.
    2. Navigate to the <your_ip>/simulation/setup_scripts directory.
    3. Perform the following command: 
      ip-setup-simulation --use-relative-paths --quartus-project=../ip_components/tb_top.qpf
  7. If you are using a simulator that requires that you open a user interface, open your target simulator.
    Note: You must select a simulator that is supported by your Quartus® Prime software version. E-tile and Agilex™ 5 devices do not support Riviera-PRO* simulator.
  8. Execute the simulation script available for your simulation in the directory.
    In the QuestaSim* simulator, type do msim_commands.do.
  9. You can modify testbench parameters from a file params_list.sv, located at <your_ip>/testbench location.
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