CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/17/2024
Public
Document Table of Contents

4.1. CPRI Intel® FPGA IP Core L2 Interface

The CPRI IP optionally communicates with an user-provided Ethernet MAC through the following signals.

Table 52.  MII and GMII SignalsEach IP core has either MII signals, GMII signals, or neither.

Signal Name

Direction

Interface

mii_rxclk Input RX MII signals

These signals are available only if you set the value of Ethernet PCS interface to MII in the CPRI parameter editor.

mii_rxreset_n Input
mii_rxdv Output
mii_rxer Output
mii_rxd[3:0] Output
mii_txclk Input TX MII signals

These signals are available only if you set the value of Ethernet PCS interface to MII in the CPRI parameter editor.

mii_txreset_n Input
mii_txen Input
mii_txer Input
mii_txd[3:0] Input
mii_tx_fifo_status[3:0] Output MII status signals

These signals are available only if you set the value of Ethernet PCS interface to MII in the CPRI parameter editor.

mii_rx_fifo_status[3:0] Output
gmii_rxclk Input RX GMII signals

These signals are available only if you set the value of Ethernet PCS interface to GMII in the CPRI parameter editor.

Note: The gmii_rxdv, gmii_rxer, and gmii_rxd[7:0] are not available if the Ethernet PCS Bypass option is turned on.
gmii_rxreset_n Input
gmii_rxdv Output
gmii_rxer Output
gmii_rxd[7:0] Output
gmii_txclk Input TX GMII signals

These signals are available only if you set the value of Ethernet PCS interface to GMII in the CPRI parameter editor.

Note: The gmii_txen, gmii_txer, and gmii_txd[7:0] are not available if the Ethernet PCS Bypass option is turned on.
gmii_txreset_n Input
gmii_txen Input
gmii_txer Input
gmii_txd[7:0] Input
gmii_txfifo_status[3:0] Output GMII status signals
These signals are available only if you set the value of Ethernet PCS interface to GMII in the CPRI parameter editor.
Note: The gmii_rxfifo_status[3:0] is not available if the Ethernet PCS Bypass option is turned on.
gmii_rxfifo_status[3:0] Output
gmii_rx_fifo_rdata Output

RX GMII Ethernet PCS bypass mode signals. These signals are available only if you set the value of Ethernet PCS interface to GMII and turn on the Ethernet PCS Bypass option in the CPRI parameter editor.

gmii_rx_fifo_rvalid Output
gmii_tx_fifo_wdata Input TX GMII Ethernet PCS bypass mode signals. These signals are available only if you set the value of Ethernet PCS interface to GMII and turn on the Ethernet PCS Bypass option in the CPRI parameter editor.
gmii_tx_fifo_wready Output
gmii_pcs_switch Input GMII Ethernet PCS switch signal. This signal is available only if you set the value of "Ethernet PCS interface" to "GMII", turn on the "Ethernet PCS Bypass" option, and turn on the "Enable run time switch of GMII PCS" option in the CPRI parameter editor.