CPRI Intel® FPGA IP User Guide

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ID 683595
Date 5/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP 2. Getting Started with the CPRI Intel® FPGA IP 3. CPRI IP Functional Description 4. CPRI Intel® FPGA IP Signals 5. CPRI Intel® FPGA IP Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support 1.3. Intel® FPGA IP Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP 1.5. CPRI IP Release Information
1.2. CPRI Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI Intel® FPGA IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP x
2.1. Installation and Licensing 2.2. Generating aCPRI Intel® FPGA IP 2.3. CPRI Intel® FPGA IP Generated Files 2.4. CPRI Intel® FPGA IP Parameters 2.5. Integrating the CPRI IP into your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Running the CPRI IP Design Example 2.8. CPRI Design Example Clocks 2.9. About the Testbench 2.10. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating the CPRI IP into your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. CPRI IP Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
2.5.7. Reference and System PLL Clock for your IP Design x
2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.5.7.2. System PLL Connections for the Agilex 5 Variations 2.5.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP
2. Getting Started with the CPRI Intel® FPGA IP
3. CPRI IP Functional Description
4. CPRI Intel® FPGA IP Signals
5. CPRI Intel® FPGA IP Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

2.9. About the Testbench

Intel® provides a demonstration testbench with the CPRI Intel® FPGA IP.

If you click Generate Example Design in the CPRI parameter editor, the Quartus® Prime software generates the demonstration testbench. The parameter editor prompts you for the desired location of the testbench.

The testbench performs the following sequence of actions with the static DUT. The listed registers offset L1_CONFIG and CM_CONFIG are in word addressing mode.

  1. Starts up CPRI rate.
  2. Enables transmission on the CPRI link by setting the tx_enable bit (bit [0]) of the CPRI IP core L1_CONFIG register at offset 0x8 (and resetting all other fields of the register).
  3. Configures the DUT at the highest possible HDLC bit rate for the CPRI line bit rate, by setting the tx_slow_cm_rate field of the CPRI CM_CONFIG register at offset 0x1C to the appropriate value.
  4. Reads the CM_CONFIG register to confirm settings.
  5. Resynchronizes BFN number if the resynchronization of CPRI radio frame number to a desired value is enabled.
  6. After the DUT and the testbench achieve frame synchronization, executes the following transactions (Only when you turn on corresponding interface in IP parameter editor):
    1. Startup Sequence Finite-State Machine (FSM) with Protocol Version and C&M Auto-Negotiation.
    2. Performs several write transactions to the IQ interface and confirms the testbench receives them on the CPRI link.
    3. Performs several write transactions to the AUX interface and confirms the testbench receives them on the CPRI link.
    4. Performs several write transactions to the Ctrl_AxC interface and confirms the testbench receives them from the DUT on the CPRI link.
    5. Performs several write transactions to the VS interface and confirms the testbench receives them from the DUT on the CPRI link.
    6. Performs several write transactions to the RTVS interface for the 10G variant, and confirms the testbench receives them form the DUT on the CPRI link.
    7. Performs several HDLC transactions and confirms the testbench receives them from the DUT on the CPRI link.
    8. Performs several write transactions to the MI or GMI interface and confirms the testbench receives them from the DUT on the CPRI link.
    9. Performs rate negotiation to new CPRI rate (switches to the next lower bit rate if available, otherwise test ends at the lowest bit rate).
    10. Repeat steps b to i.
Table 19.  Interface Signals
Signal Name Direction Type Description
clk_100 Input 1-Bit Logic 100MHz used for clocking test components, CSR and reset controls.
sampling_refclk Input 1-Bit Logic Reference clock for Agilex® 7 F-Tile IOPLL (Only for Agilex® 7 F-Tile devices).
cdr_refclk Input 1-Bit Logic Reference clock for Core IOPLL, Extended Delay Measurement PLL, and Transceiver.
cdr_refclk1 Input 1-Bit Logic Secondary reference clock for Core IOPLL, Extended Delay Measurement PLL, and Transceiver when rate negotiation is enabled (Only for Stratix® 10 H-Tile or Arria® 10 Devices).
ehip_ref_clk Input 1-Bit Logic Reference clock used to generate high speed serial clocks and data path parallel clocks in CPRI IP (Only for F-Tile and E-Tile devices).
ehip_ref_clk1 Input 1-Bit Logic Secondary reference clock used to generate high speed serial clocks and data path parallel clocks in CPRI IP when rate negotiation is enabled (Only for F-Tileand E-Tile devices).
aib_pll_refclk Input 1-Bit Logic Reference clock for Agilex® 7 F-tile and E-Tile or Stratix® 10 E-Tile AIB PLL (Only for F-Tile and E-Tile devices).
i_refclk_syspll Input 1-Bit Logic Reference clock for Agilex™ 5 system PLL.
i_refclk_xcvr Input 1-Bit Logic Transceiver reference clock for CPRI IP (Only for Agilex™ 5 devices).
reset_n Input 1-Bit Logic Global active-low reset. Not for E-tile, F-tile and Agilex™ 5 devices)
rx_serial Input 1-Bit Logic Receiver serial port.
tx_serial Output 1-Bit Logic Transmitter serial port.
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