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Release Information
LVDS SERDES IP Core Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Core Initialization and Reset
LVDS SERDES IP Core Signals
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core General Settings
LVDS SERDES IP Core Timing
LVDS SERDES IP Core Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Timing Analysis for the External PLL Mode
If you enable the Use external PLL parameter in the PLL Settings tab, the IP generation does not create clock settings for the PLL input and output. You must ensure the PLL clock settings are correct.
Some of the SERDES constraints are derived from the PLL clocks. Therefore, the external PLL clock settings must be generated before the LVDS SERDES IP core clock settings. In you project's .qsf, ensure that the line for the IOPLL IP core's .qip appears before the line for the LVDS SERDES IP core's .qip.
Add the following line in your .sdc file to ensure all the PLL clocks are derived correctly.
derive_pll_clocks -create_base_clocks