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Release Information
LVDS SERDES IP Core Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Core Initialization and Reset
LVDS SERDES IP Core Signals
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core General Settings
LVDS SERDES IP Core Timing
LVDS SERDES IP Core Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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LVDS SERDES IP Core Timing
Use the Intel® Quartus® Prime software from version 14.0.a10 onwards to generate the required timing constraint to perform proper timing analysis of the LVDS SERDES IP core in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
Timing Component | Description |
---|---|
Source Synchronous Paths | The source synchronous paths are paths where clock and data signals are passed from the transmitting devices to the receiving devices. For example:
|
Dynamic Phase Alignment Paths | A DPA block registers the I/O capture paths in soft-CDR and DPA-FIFO modes. The DPA block dynamically chooses the best phase from the PLL VCO clocks to latch the input data. |
Internal FPGA Paths | The internal FPGA paths are the paths inside the FPGA fabric:
The Timing Analyzer reports the corresponding timing margins. |
File Name | Description |
---|---|
<variation_name>_altera_lvds_core20_<quartus_version>_<random_id>.sdc | This .sdc file allows the Intel® Quartus® Prime Fitter to optimize timing margins with timing-driven compilation. The file also allows the Timing Analyzer to analyze the timing of your design. The IP core uses the .sdc for the following operations:
You can locate this file in the .qip generated during IP generation. |
sdc_util.tcl | This .tcl file is a library of functions and procedures that the .sdc uses. |