LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 7/13/2021
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Document Table of Contents
Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES IP Core Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Core Initialization and Reset LVDS SERDES IP Core Signals LVDS SERDES IP Core Parameter Settings LVDS SERDES IP Core General Settings LVDS SERDES IP Core Timing LVDS SERDES IP Core Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Core Initialization and Reset x
Initializing the LVDS SERDES IP Core in Non-DPA Mode Initializing the LVDS SERDES IP Core in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES IP Core Parameter Settings x
LVDS SERDES IP Core PLL Settings LVDS SERDES IP Core Receiver Settings LVDS SERDES IP Core Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES IP Core Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES IP Core Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES IP Core Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis for the External PLL Mode Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES IP Core Design Examples x
LVDS SERDES IP Core Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Core Simulation Design Example Combined LVDS SERDES IP Core Transmitter and Receiver Design Example LVDS SERDES IP Core Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Core Signal Interface with LVDS SERDES IP Core IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP Core and LVDS SERDES IP Core in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Bitslip

Use bitslip circuitry to insert latencies in increments of one fast clock cycle for data word alignment.

The data slips one bit for every pulse of the rx_bitslip_ctrl signal. Because it takes at least two core clock cycles to clear the undefined data, wait at least four core clock cycles before checking if the data is aligned.

After enough bitslip signals are sent to rollover the bitslip counter, the rx_bitslip_max status signal is asserted after four core clock cycles to indicate that the bitslip counter rollover point has reached its maximum counter value.

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