Visible to Intel only — GUID: sam1412833543237
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Release Information
LVDS SERDES IP Core Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Core Initialization and Reset
LVDS SERDES IP Core Signals
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core General Settings
LVDS SERDES IP Core Timing
LVDS SERDES IP Core Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412833543237
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LVDS SERDES IP Core Features
The LVDS SERDES IP core includes features for the LVDS receiver and transmitter. You can use the Intel® Quartus® Prime parameter editor to configure the LVDS SERDES IP core.
Among the features of the LVDS SERDES IP core:
- Parameterizable data channel widths
- Parameterizable SERDES factors
- Registered input and output ports
- PLL control signals
- Non-DPA mode
- DPA mode
- Soft clock data recovery (CDR) mode