Visible to Intel only — GUID: sam1412833538317
Ixiasoft
Release Information
LVDS SERDES IP Core Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Core Initialization and Reset
LVDS SERDES IP Core Signals
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core General Settings
LVDS SERDES IP Core Timing
LVDS SERDES IP Core Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412833538317
Ixiasoft
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
To migrate your ALTLVDS_TX and ALTLVDS_RX IP cores to the LVDS SERDES Intel® FPGA IP, follow these steps:
- Open your ALTLVDS_TX or ALTLVDS_RX core in the IP parameter editor.
- In the Currently selected device family, select Arria 10 or Cyclone 10 GX.
- Click Finish to open the LVDS SERDES IP core parameter editor. The parameter editor configures the LVDS SERDES IP core settings similar to the ALTLVDS_TX or ALTLVDS_RX IP core settings.
- If there are any incompatible settings between the two IP cores, select new supported settings.
- Click Finish to regenerate the IP core.
- Replace your ALTLVDS_TX or ALTLVDS_RX IP core instantiation in RTL with the LVDS SERDES IP core.
Note: The LVDS SERDES IP core port names may not match the ALTLVDS_TX or ALTLVDS_RX IP core port names. Therefore, simply changing the IP core name in the instantiation may not be sufficient.