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Release Information
LVDS SERDES IP Core Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Core Initialization and Reset
LVDS SERDES IP Core Signals
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core General Settings
LVDS SERDES IP Core Timing
LVDS SERDES IP Core Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412833580887
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LVDS SERDES IP Core PLL Settings
Parameter | Value | Description |
---|---|---|
Use external PLL | On, Off | Turn on to use an external PLL:
This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration.
Note: You must turn on this option if you want to place combined LVDS transmitter and receiver interfaces in the same I/O bank.
|
Desired inclock frequency | — | Specifies the inclock frequency in MHz. |
Actual inclock frequency | — | Displays the closest inclock frequency to the desired frequency that can source the interface. |
FPGA/PLL speed grade | — | Specifies the FPGA/PLL speed grade which determines the operation range of the PLL. |
Enable pll_areset port | On, Off | Turn on to expose the pll_areset port. You can use the pll_areset signal to reset the entire LVDS interface. |
Core clock resource type | — | Specifies onto which clock network the IP core exports an internally generated coreclock.
Note: This feature will be supported in a future version of the Intel® Quartus® Prime software. Currently, use QSF assignments to manually specify this parameter.
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