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Release Information
LVDS SERDES IP Core Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Core Initialization and Reset
LVDS SERDES IP Core Signals
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core General Settings
LVDS SERDES IP Core Timing
LVDS SERDES IP Core Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Connection between IOPLL IP Core and LVDS SERDES IP Core in External PLL Mode
Figure 18. Non-DPA LVDS Receiver Interface with IOPLL IP Core in External PLL Mode
Figure 19. DPA LVDS Receiver Interface with the IOPLL IP Core in External PLL ModeInvert the locked output port and connect it to the pll_areset port.
Figure 20. Soft-CDR LVDS Receiver Interface with the IOPLL IP Core in External PLL ModeInvert the locked output port and connect it to the pll_areset port.
Figure 21. LVDS Transmitter Interface with the IOPLL IP Core in External PLL ModeConnect the I/O PLL lvds_clk[1] and loaden[1] ports to the ext_fclk and ext_loaden ports of the LVDS transmitter.
The ext_coreclock port is automatically enabled in the LVDS SERDES IP core in external PLL mode. The Intel® Quartus® Prime compiler outputs error messages if this port is not connected as shown in the preceding figures.