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Release Information
LVDS SERDES IP Core Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Core Initialization and Reset
LVDS SERDES IP Core Signals
LVDS SERDES IP Core Parameter Settings
LVDS SERDES IP Core General Settings
LVDS SERDES IP Core Timing
LVDS SERDES IP Core Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Comparison of LVDS SERDES IP Core with Stratix® V SERDES
The LVDS SERDES IP core has similar features to the Stratix® V SERDES. The key differences are the clock network and the ubiquitous RX and TX resource in LVDS I/O banks.
Features | Intel® Arria® 10/ Intel® Cyclone® 10 GX Devices | Stratix® V Devices |
---|---|---|
Operation Frequency Range | 150 MHz - 1.6 GHz2 | |
Serialization/Deserialization Factors | 3 to 10 | |
Regular DPA and non-DPA mode | Supported | |
Clock Forwarding for Soft-CDR | Supported | |
RX Resource | Every I/O pair (Every two I/O pairs for CDR) |
Every two I/O pairs on every side without HSSI transceivers |
TX Resource | Every I/O pair | Every two I/O pairs every side without HSSI transceivers |
PLL Resource | TX channels can span three adjacent banks, driven by the IOPLL in the middle bank. RX channels are driven by the IOPLL in the same bank. |
RX and TX channels placed on one edge can be driven by the corner or center PLL. |
Number of DPA Clock Phase | 8 | |
I/O Standard | True LVDS | True LVDS, pseudo-differential output |
2 The supported operation frequency range depends on the device, speed grade, and SERDES factor. Refer to the relevant device datasheet.