Visible to Intel only — GUID: yyx1552273835296
Ixiasoft
Visible to Intel only — GUID: yyx1552273835296
Ixiasoft
3.8. Parameter Settings
Parameter | Supported Values | Default Setting | Description |
---|---|---|---|
CPRI Core Options | |||
Number of CPRI Channels in core | 1, 2, 3, 4 | 1 | Sets the number of CPRI channels included in the CPRI core. |
First RSFEC Lane |
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first_lane0 | Sets the first RS-FEC lane. This parameter is only available in IP core variations that target CPRI line rates with RS-FEC block. |
RSFEC Clocking Mode |
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fec_dir_adp_clk_0 | Sets the clocking mode for the RS-FEC block. This parameter is only available in IP core variations that target CPRI line rates with RS-FEC block. |
Configuration, Debug and Extension Options | |||
Enable Native PHY Debug Master Endpoint |
|
On | When you turn on this parameter, the Native PHY Debug Master Endpoint instantiates an Avalon® memory-mapped master and connects the Avalon® memory-mapped slave inside the PHY. This allows access to the PHY registers for debug using the Altera Transceiver Toolkit via JTAG. |
Parameter | Supported Values | Default Setting | Description |
---|---|---|---|
CPRI General Options | |||
CPRI Rate |
|
10.1376G (64b/66b) | Selects the CPRI data rate. The hard RS-FEC block is included in the core if you select 10.1376, 12.1651, and 24.33024 Gbps (64b/66b) with the RS-FEC option. |
Enable reconfiguration to 8b/10b datapath |
|
Off | Turn on this parameter if you plan to reconfigure the CPRI line rate of your channels from 64b/66b datapath rates to 8b/10b datapath rates at run-time. If this option is not enabled, the CPRI IP core uses fewer resources, and not be able to change to 8b/10b datapath rates at run-time. |
CPRI PMA Options | |||
PHY Reference frequency |
|
184.32 MHz | Support this value of the reference clock frequency for each CPRI line rate. The CPRI line rates that include 8b/10b soft PCS use a reference clock of 153.6 MHz and the CPRI line rates that include 64b/66b hard PCS use a reference clock of 184.32 MHz. This option is grayed out and always disabled in the current version of the Quartus® Prime software. |
For parameters in the PMA Adaptation tab, refer to the PMA Adaptation topic in the E-Tile Transceiver PHY User Guide.
For parameters in the Example Design tab, refer to the device specific E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration, or E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-Tile CPRI PHY, and Dynamic Reconfiguration.