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Visible to Intel only — GUID: xio1564407308326
Ixiasoft
2.10.1.1. Reset Sequence with External AIB Clocking
For details on general reset signals used during the reset, refer to Reset and Reset Signals sections.
Modes | Signals | ||
---|---|---|---|
i_csr_rst_n | i_tx_rst_n | i_rx_rst_n | |
External AIB clock enable — Master Channel |
— 26 | √ | √ |
External AIB clock enable — Slave Channel |
—26 | √ | √ |
External AIB clock disable — Master Channel |
√ 27 | √ | √ |
External AIB clock disable — Slave Channel |
√27 | √ | √ |
Use case example with 10G Master Ethernet channel and three 25G Slave Ethernet channels is shown in the Master-Slave Configuration: Option 3- Dynamic Reconfiguration clock network use case section.
For more information on PMA Analog Reset user cases, refer to the E-Tile Transceiver PHY User Guide.
For more information on the dynamic reconfiguration, refer to the Dynamic Reconfiguration Design Example User Guide.