Visible to Intel only — GUID: jso1520003744688
Ixiasoft
Visible to Intel only — GUID: jso1520003744688
Ixiasoft
2.11.14.4. PTP Reconfiguration Interfaces
The PTP reconfiguration interfaces are available when you use the 100G channel with 1 to 4 10G/25G channels, RS-FEC, and PTP variant.
Port Name | Width | Description |
---|---|---|
i_ptp_reconfig_address[p*1-9:10] |
19 bits each lane |
Control and status register address bus for PTP channel. |
i_ptp_reconfig_write[p-1:0] |
1 | PTP channel write signal asserted to write data on reconfiguration write data bus. |
i_ptp_reconfig_read[p-1:0] |
1 | PTP channel read signal asserted to start a read cycle. |
i_ptp_reconfig_writedata[p*8-1:0] |
8 |
PTP channel data to be written on a write cycle. |
o_ptp_reconfig_readdata[p*8-1:0] |
8 |
PTP channel data that was read by a read cycle. |
o_ptp_reconfig_waitrequest[p-1:0] |
1 | Avalon® memory-mapped interface stalling signal for operations on PTP control and status registers in the respective channel. The read/write cycle is only complete when this signal goes low. |