Visible to Intel only — GUID: jqt1519981542137
Ixiasoft
Visible to Intel only — GUID: jqt1519981542137
Ixiasoft
2.11.14.1. Ethernet Reconfiguration Interfaces
Asserting the i_csr_rst_n signal resets all Ethernet control and status registers, including the statistics counters; while this reset is in process, reads or writes to addresses in the Ethernet Hard IP can be delayed.
Port Name | Width | Description |
---|---|---|
i_sl_eth_reconfig_addr i_sl_eth_reconfig_addr[n-1:0] i_eth_reconfig_addr |
21 (100GE) 19 (10GE/25GE) |
Address bus for Ethernet control and status registers in the respective channel. |
i_sl_eth_reconfig_write i_sl_eth_reconfig_write[n-1:0] i_eth_reconfig_write |
1 | Write request signal for Ethernet control and status registers in the respective channel. |
i_sl_eth_reconfig_read i_sl_eth_reconfig_read[n-1:0] i_eth_reconfig_read |
1 | Read request signal for Ethernet control and status registers in the respective channel. |
i_sl_eth_reconfig_writedata i_sl_eth_reconfig_writedata[n-1:0] i_eth_reconfig_writedata |
32 | Write data for Ethernet control and status registers in the respective channel. |
i_sl_eth_reconfig_readdata i_sl_eth_reconfig_readdata[n-1:0] i_eth_reconfig_readdata |
32 | Read data from reads to Ethernet control and status registers in the respective channel. |
o_sl_eth_reconfig_readdata_valid o_sl_eth_reconfig_readdata_valid[n-1:0] o_eth_reconfig_readdata_valid |
1 | Read data from Ethernet control and status registers is valid in the respective channel. |
i_sl_eth_reconfig_waitrequest i_sl_eth_reconfig_waitrequest[n-1:0] i_eth_reconfig_waitrequest |
1 | Avalon® memory-mapped interface stalling signal for operations on Ethernet control and status registers in the respective channel. |