E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468
Date 7/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. About E-Tile Hard IP User Guide 2. About the E-Tile Hard IP for Ethernet Intel® FPGA IP Core 3. About the E-Tile CPRI PHY Intel® FPGA IP 4. Supported Tools 5. E-Tile Hard IP User Guide Archives
2. About the E-Tile Hard IP for Ethernet Intel® FPGA IP Core x
2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP Supported Features 2.2. E-Tile Hard IP for Ethernet Intel® FPGA IP Overview 2.3. IP Core Device Family and Speed Grade Support 2.4. IP Core Verification 2.5. Resource Utilization 2.6. Release Information 2.7. Getting Started 2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters 2.9. Functional Description 2.10. Reset 2.11. Interfaces and Signals 2.12. Register Descriptions 2.13. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Core
2.3. IP Core Device Family and Speed Grade Support x
2.3.1. E-Tile Hard IP for Ethernet Intel® FPGA IP Device Family Support 2.3.2. E-Tile Hard IP for Ethernet Intel® FPGA IP Device Speed Grade Support
2.4. IP Core Verification x
2.4.1. Simulation Environment 2.4.2. Compilation Checking 2.4.3. Hardware Testing
2.7. Getting Started x
2.7.1. Installing and Licensing Intel® FPGA IP Cores 2.7.2. Specifying the IP Core Parameters and Options 2.7.3. Generated File Structure 2.7.4. Integrating Your IP Core in Your Design 2.7.5. IP Core Testbenches 2.7.6. Compiling the Full Design
2.7.1. Installing and Licensing Intel® FPGA IP Cores x
2.7.1.1. Intel® FPGA IP Evaluation Mode
2.7.4. Integrating Your IP Core in Your Design x
2.7.4.1. Channel Placement 2.7.4.2. Pin Assignments 2.7.4.3. Clock Requirements 2.7.4.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.4.5. SDC for Multiple E-Tile Instances
2.7.4.1. Channel Placement x
2.7.4.1.1. Guidelines and Restrictions for 24-bonded Channels Variant 2.7.4.1.2. Guidelines and Restrictions for 16-bonded Channels Variant
2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters x
2.8.1. Parameter Editor Parameters 2.8.2. RTL Parameters
2.9. Functional Description x
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC 2.9.2. 1588 Precision Time Protocol Interfaces 2.9.3. PCS, OTN, FlexE, and Custom PCS Modes 2.9.4. Auto-Negotiation and Link Training 2.9.5. TX and RX RS-FEC 2.9.6. PMA Direct Mode 2.9.7. Dynamic Reconfiguration 2.9.8. Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example 2.9.9. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example 2.9.10. Ethernet Adaptation Flow with PTP or with External AIB Clocking 2.9.11. Ethernet Adaptation Flow with Non-external AIB Clocking
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC x
2.9.1.1. MAC TX Datapath 2.9.1.2. MAC RX Datapath 2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 2.9.1.4. Pause Control and Generation Interface 2.9.1.5. Pause Control Frame Filtering 2.9.1.6. Link Fault Signaling 2.9.1.7. Order of Ethernet Transmission
2.9.1.1. MAC TX Datapath x
2.9.1.1.1. TX Preamble, Start, and SFD Insertion 2.9.1.1.2. Source Address Insertion 2.9.1.1.3. Length/Type Field Processing 2.9.1.1.4. Frame Padding 2.9.1.1.5. Frame Check Sequence (CRC-32) Insertion 2.9.1.1.6. Inter-Packet Gap Generation and Insertion
2.9.1.2. MAC RX Datapath x
2.9.1.2.1. RX Preamble Processing 2.9.1.2.2. RX Strict SFD Checking 2.9.1.2.3. RX FCS Checking 2.9.1.2.4. RX Malformed Packet Handling 2.9.1.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 2.9.1.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 2.9.1.2.7. Inter-Packet Gap
2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
2.9.1.3.1. Conditions Triggering XOFF Frame Transmission 2.9.1.3.2. Conditions Triggering XON Frame Transmission
2.9.1.6. Link Fault Signaling x
2.9.1.6.1. Determining Link Fault Condition
2.9.2. 1588 Precision Time Protocol Interfaces x
2.9.2.1. Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP 2.9.2.2. PTP Timestamp Accuracy 2.9.2.3. PTP Transmit Functionality 2.9.2.4. PTP Receive Functionality 2.9.2.5. External Time-of-Day Module for 1588 PTP Variations 2.9.2.6. PTP Timestamp and TOD Formats 2.9.2.7. 10G/25G TX and RX Unit Interval Adjustment 2.9.2.8. 10G/25G TX and RX PTP Extra Latency 2.9.2.9. 100G PTP TX User Flow 2.9.2.10. 100G PTP RX User Flow 2.9.2.11. 100G RX Virtual Lane Offset Calculation for No FEC Variants 2.9.2.12. 100G UI Adjustment 2.9.2.13. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 2.9.2.14. PTP System Considerations 2.9.2.15. Logic Lock Regions Requirements for PTP Accuracy Advanced Mode
2.9.3. PCS, OTN, FlexE, and Custom PCS Modes x
2.9.3.1. PCS Only Mode 2.9.3.2. OTN Mode 2.9.3.3. FlexE Mode 2.9.3.4. Custom PCS Mode
2.10. Reset x
2.10.1. Reset Sequence
2.10.1. Reset Sequence x
2.10.1.1. Reset Sequence with External AIB Clocking
2.11. Interfaces and Signals x
2.11.1. TX MAC Interface to User Logic 2.11.2. RX MAC Interface to User Logic 2.11.3. TX PCS Interface to User Logic 2.11.4. RX PCS Interface to User Logic 2.11.5. FlexE and OTN Mode TX Interface 2.11.6. FlexE and OTN Mode RX Interface 2.11.7. TX Custom PCS Interface to User Logic 2.11.8. RX Custom PCS Interface to User Logic 2.11.9. PMA Direct Interface 2.11.10. Custom Rate Interface 2.11.11. Deterministic Latency Interface 2.11.12. 1588 PTP Interface 2.11.13. Ethernet Link and Transceiver Signals 2.11.14. Reconfiguration Interfaces and Signals 2.11.15. Miscellaneous Status and Debug Signals 2.11.16. Reset Signals 2.11.17. Clocks
2.11.14. Reconfiguration Interfaces and Signals x
2.11.14.1. Ethernet Reconfiguration Interfaces 2.11.14.2. Transceiver Reconfiguration Interfaces 2.11.14.3. RS-FEC Reconfiguration Interfaces 2.11.14.4. PTP Reconfiguration Interfaces
2.11.17. Clocks x
2.11.17.1. Asynchronous Adapter Clock in 10G/25G Mode 2.11.17.2. Asynchronous Adapter Clock in 100G Mode 2.11.17.3. Clock Network Use Cases
2.11.17.3. Clock Network Use Cases x
2.11.17.3.1. Single 25G Ethernet Channel (with FEC) 2.11.17.3.2. Single 10G Ethernet Channel (without FEC) 2.11.17.3.3. Four 25G Ethernet Channels (with FEC) within a Single FEC Block 2.11.17.3.4. Ethernet 25G x 4 (FEC Off) 2.11.17.3.5. 10G/25G Ethernet Channel with Basic PTP Accuracy Mode 2.11.17.3.6. 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode 2.11.17.3.7. 100G Ethernet with Aggregated FEC 2.11.17.3.8. 100G Ethernet with PTP 2.11.17.3.9. Single 25G Synchronous Ethernet Channel 2.11.17.3.10. Multiple 25G Synchronous Ethernet Channels
2.12. Register Descriptions x
2.12.1. Auto Negotiation and Link Training Registers 2.12.2. PHY Registers 2.12.3. TX MAC Registers 2.12.4. RX MAC Registers 2.12.5. Pause and Priority- Based Flow Control Registers 2.12.6. TX Statistics Counter Registers 2.12.7. RX Statistics Counter Registers 2.12.8. 1588 PTP Registers 2.12.9. RS-FEC Registers 2.12.10. PMA Registers
2.12.1. Auto Negotiation and Link Training Registers x
2.12.1.1. ANLT Sequencer Config 2.12.1.2. ANLT Sequencer Status 2.12.1.3. Auto Negotiation Config Register 1 2.12.1.4. Auto Negotiation Config Register 2 2.12.1.5. Auto Negotiation Status Register 2.12.1.6. Auto Negotiation Config Register 3 2.12.1.7. Auto Negotiation Config Register 4 2.12.1.8. Auto Negotiation Config Register 5 2.12.1.9. Auto Negotiation Config Register 6 2.12.1.10. Auto Negotiation Status Register 1 2.12.1.11. Auto Negotiation Status Register 2 2.12.1.12. Auto Negotiation Status Register 3 2.12.1.13. Auto Negotiation Status Register 4 2.12.1.14. Auto Negotiation Status Register 5 2.12.1.15. AN Channel Override 2.12.1.16. Consortium Next Page Override 2.12.1.17. Consortium Next Page Link Partner Status 2.12.1.18. Link Training Config Register 1 2.12.1.19. Link Training Status Register 1 2.12.1.20. Link Training Config Register for Lane 0 2.12.1.21. Link Training Config Register for Lane 1 2.12.1.22. Link Training Config Register for Lane 2 2.12.1.23. Link Training Config Register for Lane 3
2.12.2. PHY Registers x
2.12.2.1. PHY Module Revision ID 2.12.2.2. PHY Scratch Register 2.12.2.3. Loopback Mode 2.12.2.4. PHY Configuration 2.12.2.5. Reset Sequencer RS-FEC Disable 2.12.2.6. RX CDR PLL Locked 2.12.2.7. TX Datapath Ready 2.12.2.8. Frame Errors Detected 2.12.2.9. Clear Frame Errors 2.12.2.10. RX PCS Status for AN/LT 2.12.2.11. PCS Error Injection 2.12.2.12. Alignment Marker Lock 2.12.2.13. Change in RX PCS Deskew Status 2.12.2.14. BER Count 2.12.2.15. Transfer Ready (AIB reset) Status for EHIP, ELANE, and PTP Channels 2.12.2.16. EHIP, ELANE, and RS-FEC Reset Status 2.12.2.17. PCS Virtual Lane 0 2.12.2.18. PCS Virtual Lane 1 2.12.2.19. PCS Virtual Lane 2 2.12.2.20. PCS Virtual Lane 3 2.12.2.21. Recovered Clock Frequency in KHz 2.12.2.22. TX Clock Frequency in KHz 2.12.2.23. Configuration Fields for TX PLD 2.12.2.24. Status for TX PLDs 2.12.2.25. Status for Dynamic Deskew Buffer 2.12.2.26. Configuration for RX PLD Block 2.12.2.27. Configuration for RX PCS 2.12.2.28. BIP Counter 0 2.12.2.29. BIP Counter 1 2.12.2.30. BIP Counter 2 2.12.2.31. BIP Counter 3 2.12.2.32. BIP Counter 4 2.12.2.33. BIP Counter 5 2.12.2.34. BIP Counter 6 2.12.2.35. BIP Counter 7 2.12.2.36. BIP Counter 8 2.12.2.37. BIP Counter 9 2.12.2.38. BIP Counter 10 2.12.2.39. BIP Counter 11 2.12.2.40. BIP Counter 12 2.12.2.41. BIP Counter 13 2.12.2.42. BIP Counter 14 2.12.2.43. BIP Counter 15 2.12.2.44. BIP Counter 16 2.12.2.45. BIP Counter 17 2.12.2.46. BIP Counter 18 2.12.2.47. BIP Counter 19 2.12.2.48. Timer Window for Hi-BER Checks 2.12.2.49. Hi-BER Frame Errors 2.12.2.50. Error Block Count 2.12.2.51. Deskew Depth 0 2.12.2.52. Deskew Depth 1 2.12.2.53. Deskew Depth 2 2.12.2.54. Deskew Depth 3 2.12.2.55. RX PCS Test Error Count
2.12.3. TX MAC Registers x
2.12.3.1. TX MAC Module Revision ID 2.12.3.2. TX MAC Scratch Register 2.12.3.3. Link Fault Configuration 2.12.3.4. IPG Words to remove per Alignment Marker Period 2.12.3.5. Maximum TX Frame Size 2.12.3.6. TX MAC Configuration 2.12.3.7. EHIP TX MAC Feature Configuration 2.12.3.8. TX MAC Source Address Lower Bytes 2.12.3.9. TX MAC Source Address Higher Bytes
2.12.4. RX MAC Registers x
2.12.4.1. RX MAC Module Revision ID 2.12.4.2. RX MAC Scratch Register 2.12.4.3. Maximum RX Frame Size 2.12.4.4. RX CRC Forwarding 2.12.4.5. Link Fault Status 2.12.4.6. RX MAC Configuration 2.12.4.7. EHIP RX MAC Feature Configuration
2.12.5. Pause and Priority- Based Flow Control Registers x
2.12.5.1. TXSFC Module Revision ID 2.12.5.2. TX SFC Scratch Register 2.12.5.3. Enable TX Pause Ports 2.12.5.4. TX Pause Request 2.12.5.5. Enable Automatic TX Pause Retransmission 2.12.5.6. Retransmit Holdoff Quanta 2.12.5.7. Retransmit Pause Quanta 2.12.5.8. Enable TX XOFF 2.12.5.9. Enable Uniform Holdoff 2.12.5.10. Set Uniform Holdoff 2.12.5.11. Lower 4 bytes of the Destination address for Flow Control 2.12.5.12. Higher 2 bytes of the Destination address for Flow Control 2.12.5.13. Lower 4 bytes of the Source address for Flow Control frames 2.12.5.14. Higher 2 bytes of the Source address for Flow Control frames 2.12.5.15. TX Flow Control Feature Configuration 2.12.5.16. Pause Quanta 0 2.12.5.17. Pause Quanta 1 2.12.5.18. Pause Quanta 2 2.12.5.19. Pause Quanta 3 2.12.5.20. Pause Quanta 4 2.12.5.21. Pause Quanta 5 2.12.5.22. Pause Quanta 6 2.12.5.23. Pause Quanta 7 2.12.5.24. PFC Holdoff Quanta 0 2.12.5.25. PFC Holdoff Quanta 1 2.12.5.26. PFC Holdoff Quanta 2 2.12.5.27. PFC Holdoff Quanta 3 2.12.5.28. PFC Holdoff Quanta 4 2.12.5.29. PFC Holdoff Quanta 5 2.12.5.30. PFC Holdoff Quanta 6 2.12.5.31. PFC Holdoff Quanta 7 2.12.5.32. RXSFC Module Revision ID 2.12.5.33. RXSFC Scratch Register 2.12.5.34. Enable RX Pause Frame Processing 2.12.5.35. Forward Flow Control Frames 2.12.5.36. Lower 4 bytes of the Destination address for RX Pause Frames 2.12.5.37. Higher 2 bytes of the Destination address for RX Pause Frames 2.12.5.38. RX Flow Control Feature Configuration
2.12.6. TX Statistics Counter Registers x
2.12.6.1. TX Statistics Registers
2.12.7. RX Statistics Counter Registers x
2.12.7.1. RX Statistics Registers
3. About the E-Tile CPRI PHY Intel® FPGA IP x
3.1. Supported Features 3.2. E-Tile CPRI PHY Intel® FPGA IP Overview 3.3. E-Tile CPRI PHY Device Family Support 3.4. Resource Utilization 3.5. Release Information 3.6. E-Tile CPRI PHY Intel FPGA IP Core Device Speed Grade Support 3.7. Getting Started 3.8. Parameter Settings 3.9. Functional Description 3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals 3.11. Registers 3.12. Document Revision History for the E-Tile CPRI PHY Intel FPGA IP
3.7. Getting Started x
3.7.1. Installing and Licensing Intel® FPGA IP Cores 3.7.2. Specifying the IP Core Parameters and Options 3.7.3. Generated File Structure 3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement 3.7.5. IP Core Testbenches 3.7.6. Compiling the Full Design
3.7.1. Installing and Licensing Intel® FPGA IP Cores x
3.7.1.1. Intel® FPGA IP Evaluation Mode
3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement x
3.7.4.1. One 24.33024 Gbps channel with RS-FEC 3.7.4.2. Two 24.33024 Gbps Channel with RS-FEC 3.7.4.3. Three 24.33024 Gbps channels with RS-FEC 3.7.4.4. Four 24.33024 Gbps channels with RS-FEC 3.7.4.5. Restrictions
3.9. Functional Description x
3.9.1. CPRI PHY Functional Blocks 3.9.2. Dynamic Reconfiguration
3.9.1. CPRI PHY Functional Blocks x
3.9.1.1. E-Tile Native PHY 3.9.1.2. Soft Reset Sequencer 3.9.1.3. Latency Measurement
3.9.1.3. Latency Measurement x
3.9.1.3.1. Deterministic Latency Calculation
3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals x
3.10.1. Clock Signals 3.10.2. TX MII Interface 3.10.3. RX MII Interface 3.10.4. TX 8B/10B Interface 3.10.5. RX 8B/10B Interface 3.10.6. Status Interface for 64B/66B Line Rate 3.10.7. Status Interface for 8B/10B Line Rate 3.10.8. Serial I/O Pins 3.10.9. Reconfiguration Interfaces ( Avalon® Memory-Mapped Interface)
3.10.9. Reconfiguration Interfaces ( Avalon® Memory-Mapped Interface) x
3.10.9.1. CPRI PHY Reconfiguration Interface 3.10.9.2. Transceiver Reconfiguration Interface 3.10.9.3. RS-FEC Reconfiguration Interface
3.11. Registers x
3.11.1. PHY Registers 3.11.2. CPRI PHY Registers 3.11.3. PMA Registers 3.11.4. RS-FEC Registers
3.11.3. PMA Registers x
3.11.3.1. Minimizing PMA Adaptation Time
4. Supported Tools x
4.1. E-Tile Channel Placement Tool 4.2. Ethernet Toolkit Overview 4.3. Document Revision History for the E-Tile Channel Placement Tool and the Ethernet Link Inspector
4.2. Ethernet Toolkit Overview x
4.2.1. Features
1. About E-Tile Hard IP User Guide
2. About the E-Tile Hard IP for Ethernet Intel® FPGA IP Core
3. About the E-Tile CPRI PHY Intel® FPGA IP
4. Supported Tools
5. E-Tile Hard IP User Guide Archives

2.12.8. 1588 PTP Registers

The 1588 PTP registers together with the 1588 PTP signals process and provide Precision Time Protocol (PTP) timestamp information as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard. The 1588 PTP module provides you the support to implement the 1588 Precision Time Protocol in your design.

Table 76.  TX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xA00 TXPTP_REVID [31:0] IP core revision ID.

0x1111_2015

 RO
0xA01 TXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xA05 TX_PTP_CLK_PERIOD [19:0]

20-bit register holding the datapath clock period in the IEEE 1588v2 format. This value is used to estimate delays through the datapath.

Period of the 402.83 MHz EHIP clock in 1588v2 format.

Bits[19:16]: nanoseconds (ns)

Bits[15:0]: fractions of nanosecond

 0x27B81 RW
0xA0A TX_PTP_EXTRA_LATENCY [31:0] User-defined extra latency the IP core adds to outgoing TX 1-step and 2-step timestamps.

[31]: Sign bit, set to 1 for negative extra latency

Bits[30:16]: Extra latency in nanoseconds

Bits[15:0]: Extra latency in fractions of nanosecond (value/17'h10000)

For example, to set a TX extra latency of +2.5 ns, set tx_ptp_extra_latency to 32'h00028000.

32'b0 RW
0xA0D PTP_DEBUG [31:0]

Controls a small number of PTP debug features.

  • Bit[0] = 1: instead of inserting PTP field values in TX packets when executing PTP TX 1-step commands, insert fixed values
    • Insert 8'hAA in all bytes that would have been used for timestamp bytes
    • Insert 8'hBB in all bytes that would have been used for correction field bytes
    • Insert 8'hCC in all bytes that would have been used for Extension bytes
  • Bit[31:1]: Reserved
 0x0 RW
0xB10 TX_UI_REG [31:0] Sets the time of a single serial bit on the TX Serial interface.

Sets the time for a single TX serial bit. This time is used to generate TX timestamp estimates.

  • Bit[31:24]: Nanoseconds field for the time of a single serial TX bit
  • [23:0]: Fractional nanoseconds field for the time of a single serial TX bit
0x9EE01/ 0x18D302 RW
0xB11 RX_UI_REG [31:0] Sets the time of a single serial bit on the RX Serial interface.

Sets the time for a single RX serial bit. This time is used to generate RX timestamp estimates.

  • Bit[31:24]: Nanoseconds field for the time of a single serial RX bit
  • [23:0]: Fractional nanoseconds field for the time of a single serial RX bit
0x9EE01/ 0x18D302 RW
Table 77.  RX 1588 PTP Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0xB00 RXPTP_REVID [31:0] IP core revision ID.

0x1111_2015

 RO
0xB01 RXPTP_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0xB06 RX_PTP_EXTRA_LATENCY [31:0]

32-bit specifying extra latency that EHIP adds to the incoming RX timestamps.

  • Bit[31]: Sign bit, set to 1 for negative latency
  • Bits[30:16]: Extra latency in nanoseconds
  • Bits[15:0]: Extra latency in fractions of a nanosecond

For example, to set an RX extra latency of 5.00 ns, set rx_ptp_extra_latency to 32'h00050000.

32'b0 RW
Table 78.  10G/25G PTP PPM UI Adjustment Registers

Addr

Name

Bit

Description

HW Default Value

Access

0xB19 TAM_SNAPSHOT [0] Time value control register.

When set, the values of the reference time value and AM count number are recorded in TX_TAM and TX_COUNT registers.

0x0

 RW
0xB1A TX_TAM_L [31:0] This register represents the lower 32-bits of the TX TAM value.

TX_TAM[31:0]:

  • Bits[31:16]: Nanosecond field for the LSB
  • Bits[15:0]: Fractional nanoseconds field
0x0 RO
0xB1B TX_TAM_H [15:0] This register represents the upper 16-bits of the TX_TAM value.

TX_TAM[47:32]: Nanosecond field for the MSB

0x0 RO
0xB1C TX_COUNT [15:0] Contains the TX_AM count value. 0x0 RO
0xB1D RX_TAM_L [31:0] This register represents the lower 32-bits of the RX TAM value.

RX_TAM[31:0]:

  • Bits[31:16]: Nanosecond field for the LSB
  • Bits[15:0]: Fractional nanoseconds field
0x0 RO
0xB1E RX_TAM_H [15:0] This register represents the upper 16-bits of the RX_TAM value.

RX_TAM[47:32]: Nanosecond field for the MSB

0x0 RO
0xB1F RX_COUNT [15:0] Contains the RX_AM count value. 0x0 RO
Table 79.  100G PTP PPM UI Adjustment Registers
Addr Name Description HW Default Value Access
0xC00 mlptp_tx_ui UI time in ns and fns. Sets the time for a single TX serial bit. This time is used to generate TX timestamp estimates.
  • Bit [31:24]: Nanoseconds field for the time of a single serial TX bit
  • Bit [23:0]: Fractional nanoseconds field for the time of a single serial TX bit
0x0009 EE01 RW
0xC01 mlptp_rx_ui UI time in ns and fns. Sets the time for a single RX serial bit. This time is used to generate RX timestamp estimates.
  • Bit [31:24]: Nanoseconds field for the time of a single serial RX bit
  • Bit [23:0]: Fractional nanoseconds field for the time of a single serial RX bit
0x0CCC CCCD RW
0xC10 vl0_offset_data_0
  • Bit [31]: vl_offset_data_valid—Indicate VL Offset Data is valid to be used for calculation
  • Bit [23:10]: AM_COUNT—Alignment Marker Count
  • Bit [9:5]: BA_POS—Block Aligner Position
  • Bit [4:3]: BA_PHASE—Block Aligner Phase
  • Bit [2:0]: GBSTATE—Gearbox state for the selected virtual lane
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx x000 RO
0xC12 vl1_offset_data_0
0xC14 vl2_offset_data_0
0xC16 vl3_offset_data_0
0xC18 vl4_offset_data_0
0xC1A vl5_offset_data_0
0xC1C vl6_offset_data_0
0xC1E vl7_offset_data_0
0xC20 vl8_offset_data_0
0xC22 vl9_offset_data_0
0xC24 vl10_offset_data_0
0xC26 vl11_offset_data_0
0xC28 vl12_offset_data_0
0xC2A vl13_offset_data_0
0xC2C vl14_offset_data_0
0xC2E vl15_offset_data_0
0xC30 vl16_offset_data_0
0xC32 vl17_offset_data_0
0xC34 vl18_offset_data_0
0xC36 vl19_offset_data_0
0xC11 vl0_offset_data_1
  • Bit [31]: vl_offset_data_valid—Indicate VL Offset Data is valid to be used for calculation.
  • Bit [11:10]: LOCAL_PL—Local Physical Lane Index Number
  • Bit [9:5]: REMOTE_VL—Remote Virtual Lane Index Number
  • Bit [4:0]: LOCAL_VL—Local Virtual Lane Index Number
0bxxxx xxxx xxxx xxxx xxxx xxxx xxx0 0000 RO
0xC13 vl1_offset_data_1
0xC15 vl2_offset_data_1
0xC17 vl3_offset_data_1
0xC19 vl4_offset_data_1
0xC1B vl5_offset_data_1
0xC1D vl6_offset_data_1
0xC1F vl7_offset_data_1
0xC21 vl8_offset_data_1
0xC23 vl9_offset_data_1
0xC25 vl10_offset_data_1
0xC27 vl11_offset_data_1
0xC29 vl12_offset_data_1
0xC2B vl13_offset_data_1
0xC2D vl14_offset_data_1
0xC2F vl15_offset_data_1
0xC31 vl16_offset_data_1
0xC33 vl17_offset_data_1
0xC35 vl18_offset_data_1
0xC37 vl19_offset_data_1
0xC40 vl0_offset_cfg_0
  • Bit [6:5]: LOCAL_PL—Physical Lane for the VL Offset
  • Bit [4:0]: REMOTE_VL—Virtual Lane Index for the VL Offset
0bxxxx xxxx xxxx xxxx xxxx xxxx xxx0 0000 RW
0xC42 vl1_offset_cfg_0
0xC44 vl2_offset_cfg_0
0xC46 vl3_offset_cfg_0
0xC48 vl4_offset_cfg_0
0xC4A vl5_offset_cfg_0
0xC4C vl6_offset_cfg_0
0xC4E vl7_offset_cfg_0
0xC50 vl8_offset_cfg_0
0xC52 vl9_offset_cfg_0
0xC54 vl10_offset_cfg_0
0xC56 vl11_offset_cfg_0
0xC58 vl12_offset_cfg_0
0xC5A vl13_offset_cfg_0
0xC5C vl14_offset_cfg_0
0xC5E vl15_offset_cfg_0
0xC60 vl16_offset_cfg_0
0xC62 vl17_offset_cfg_0
0xC64 vl18_offset_cfg_0
0xC66 vl19_offset_cfg_0
0xC41 vl0_offset_cfg_1
  • Bit [31]: sign_bit—Sign bit.
  • Bit [30:16]: offset_ns—Virtual lane offset (nanoseconds)
  • Bit [15:0]: offset_frac_ns—Virtual lane offset (fractional nanoseconds)
  RW
0xC43 vl1_offset_cfg_1
0xC45 vl2_offset_cfg_1
0xC47 vl3_offset_cfg_1
0xC49 vl4_offset_cfg_1
0xC4B vl5_offset_cfg_1
0xC4D vl6_offset_cfg_1
0xC4F vl7_offset_cfg_1
0xC51 vl8_offset_cfg_1
0xC53 vl9_offset_cfg_1
0xC55 vl10_offset_cfg_1
0xC57 vl11_offset_cfg_1
0xC59 vl12_offset_cfg_1
0xC5B vl13_offset_cfg_1
0xC5D vl14_offset_cfg_1
0xC5F vl15_offset_cfg_1
0xC61 vl16_offset_cfg_1
0xC63 vl17_offset_cfg_1
0xC65 vl18_offset_cfg_1
0xC67 vl19_offset_cfg_1
0xC70 mlptp_tam_snapshot Time value control register. When set, the values of the reference time value and AM count number are recorded TX and RX registers.
Request TAM snapshot to calculate unit interval (ui). TX and RX TAM snapshot are independent:
  • Bit [0]: tx_tam_snapshot

    Set this bit to 1'b1 to request TX TAM snapshot. Asserting this bit generates a single pulse to hardware.

  • Bit [1]: rx_tam_snapshot

    Set this bit to 1'b1 to request RX TAM snapshot. Asserting this bit generates a single pulse to hardware.

0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 RW
0xC71 mlptp_tx_tam_l

TX TAM lower bits. Bit [31:0] of TAM

Result returned upon TAM snapshot request, consists of TAM partial bits.

0x0000 0000 RO
0xC72 mlptp_tx_tam_h

TX TAM upper bits. Bit [15:0] of TAM

Result returned upon TAM snapshot request, consists of TAM partial bits.

0xXXXX 0000 RO
0xC73 mlptp_tx_am_count TX TAM counter. Bit [15:0]—16 bits of TAM counter.

Result returned upon TAM snapshot request, consists of TAM partial bits.

0xXXXX 0000 RO
0xC74 mlptp_rx_tam_l

RX TAM lower bits. Bit [31:0] of TAM

Result returned upon TAM snapshot request, consists of TAM partial bits.

0x0000 0000 RO
0xC75 mlptp_rx_tam_h

RX TAM upper bits. Bit [15:0] of TAM

Result returned upon TAM snapshot request, consists of TAM partial bits.

0xXXXX 0000 RO
0xC76 mlptp_rx_am_count RX TAM counter. Bit [15:0]—16 bits of TAM counter.

Result returned upon TAM snapshot request, consists of TAM partial bits.

0xXXXX 0000 RO
0xC77 mlptp_tx_ref_lane Physical lane that TAM associates with.
  • Bit [2:0]: tx_ref_lane
    TX reference lane—3 bit number of TX physical lane (any can be reference):
    • Resetting TX datapath, or the entire core clears this bit to 0

Only applicable to multi-lane designs.

0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx x000 WO
0xC78 mlptp_rx_ref_lane Physical lane that TAM associates with.
  • Bit [2:0]: rx_ref_lane
    RX reference lane—3 bit number of RX physical lane which packet last arrives at.
    • rx_pcs_fully_aligned deassertion clears the bits to 0
    • Resetting RX datapath or the entire core also clears the bits to 0

Only applicable to multi-lane designs.

0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx x000 WO
0xC79 mlptp_tx_user_cfg Indicates user has completed all necessary TX configuration:
  • Bit [0] = 1 means configured.
  • Bit [0] = 0 means not configured yet:
    • has programmed TX extra latency to Hard IP
    • has programmed TX VL offset to Hard IP (Multi-lane variant only)
Register value is automatically cleared in the following condition:
  • tx_lanes_stable deassertion
  • Resetting TX datapath or the entire core
 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 WO
0xC7A mlptp_rx_user_cfg Indicates user has completed all necessary RX configuration:
  • Bit [0] = 1 means configured.
  • Bit [0] = 0 means not configured yet:
    • has programmed RX extra latency to Hard IP
    • has programmed RX VL offset to Hard IP (Multi-lane variant only)
Register value is automatically cleared in the following condition:
  • rx_pcs_fully_aligned deassertion
  • Resetting RX datapath or the entire core
 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 WO
0xC7B mlptp_status PTP Status Register:
  • Bit [3]: rx_ptp_ready (RX PTP Ready). 1'b1 means ready.
  • Bit [2]: tx_ptp_ready (TX PTP Ready). 1'b1 means ready.
  • Bit [1]: rx_ptp_offset_data_valid (RX calculation data valid/ready to read). 1'b1 means valid.
  • Bit [0]: tx_ptp_offset_data_valid (TX calculation data valid/ready to read). 1'b1 means valid.
0xXXXX XXX0 RO
0xC7C mlptp_tx_const_delay Constant delay value used in TAM adjustment calculation. Constant delay for specific physical lane.
  • Bit [31:0]: data_constdelay
0x0000 0000 RO
0xC7D mlptp_rx_const_delay Constant delay value used in TAM adjustment calculation. Constant delay for specific physical lane.
  • Bit [31:0]: data_constdelay
0x0000 0000 RO
0xC7E mlptp_tx_l0_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC7F mlptp_rx_l0_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC80 mlptp_tx_l0_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
 0xX000 0000 RO
0xC81 mlptp_rx_l0_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
0xX000 0000 RO
0xC82 mlptp_tx_l0_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
0xC83 mlptp_rx_l0_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
0xC84 mlptp_tx_l1_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC85 mlptp_rx_l1_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC86 mlptp_tx_l1_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
0xX000 0000 RO
0xC87 mlptp_rx_l1_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
0xX000 0000 RO
0xC88 mlptp_tx_l1_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
0xC89 mlptp_rx_l1_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
0xC8A mlptp_tx_l2_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC8B mlptp_rx_l2_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC8C mlptp_tx_l2_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
0xX000 0000 RO
0xC8D mlptp_rx_l2_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
0xX000 0000 RO
0xC8E mlptp_tx_l2_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
0xC8F mlptp_rx_l2_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
0xC90 mlptp_tx_l3_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC91 mlptp_rx_l3_offset Time offset value used in TAM adjustment calculation. Time offset for specific physical lane.
  • Bit [31:0]: data_offset
0x0000 0000 RO
0xC92 mlptp_tx_l3_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
0xX000 0000 RO
0xC93 mlptp_rx_l3_time Time value used in TAM adjustment calculation. Marker time for specific physical lane.
  • Bit [27:0]: data_time
0xX000 0000 RO
0xC94 mlptp_tx_l3_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
0xC95 mlptp_rx_l3_wire_dly Wire delay value used in TAM adjustment calculation. Wire delay for specific physical lane.
  • Bit [19:0]: data_wiredelay
0xXXX0 0000 RO
Level Two Title