Visible to Intel only — GUID: zjj1521006267761
Ixiasoft
Visible to Intel only — GUID: zjj1521006267761
Ixiasoft
2.10. Reset
- eio_sys_rst
- soft_tx_rst
- soft_rx_rst
- i_csr_rst_n (100G) / i_sl_csr_rst_n (10G/25G)
- i_tx_rst_n (100G) / i_sl_tx_rst_n (10G/25G)
- i_rx_rst_n (100G) / i_sl_rx_rst_n (10G/25G)
Asserting the external hard reset i_csr_rst_n/i_sl_csr_rst_n or the soft reset eio_sys_rst returns all Ethernet registers to their original values, including the statistics counters. An additional dedicated reset signal, i_reconfig_reset, resets the transceiver reconfiguration, Ethernet reconfiguration interfaces, and some Ethernet soft registers.
Reset Signal | Block | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
TX EMIB Interface | TX MAC | TX PCS | TX FEC | TX PMA Interface | TX Statistics | RX EMIB Interface | RX MAC | RX PCS | RX FEC | RX PMA Interface | RX Statistics | |
i_sl_csr_rst_n |
√ |
√ |
√ |
— |
√ |
√ |
√ |
√ |
√ |
— |
√ |
√ |
i_csr_rst_n eio_sys_rst |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
i_sl_tx_rst_n soft_tx_rst 23 |
— |
√ |
√ |
— |
— |
— |
— |
— |
— |
— |
— |
— |
i_tx_rst_n soft_tx_rst 24 |
— |
√ |
√ |
√ |
— |
— |
— |
— |
— |
— |
— |
— |
i_sl_rx_rst_n soft_rx_rst 23 |
— |
— |
— |
— |
— |
— |
— |
√ |
√ |
— |
— |
— |
i_rx_rst_n soft_rx_rst 24 |
— |
— |
— |
— |
— |
— |
— |
√ |
√ |
√ |
— |
— |
soft_clear_tx_stats | — |
— |
— |
— |
— |
√ |
— |
— |
— |
— |
— |
— |
soft_clear_rx_stats | — |
— |
— |
— |
— |
— |
— |
— |
— |
— |
— |
√ |
The general reset signals reset the following functions:
- soft_tx_rst, i_tx_rst_n/i_sl_tx_rst_n:
- Resets the IP core in the TX direction.
- Resets TX PCS, TX MAC, and TX PMA interface.
- This reset leads to deassertion of the o_tx_lanes_stable output signal.
- In Ethernet Toolkit, perform this reset using the TX MAC and PCS Reset.
- soft_rx_rst, i_rx_rst_n/i_sl_rx_rst_n:
- Resets the IP core in the RX direction.
- Resets RX PCS, and RX MAC.
- This reset leads to deassertion of the o_rx_pcs_ready output signal.
- In Ethernet Toolkit, perform this reset using the RX MAC and PCS Reset.
- eio_sys_rst, i_csr_rst_n/i_sl_csr_rst_n:
- Resets the IP core. i_csr_rst_n signal is edge sensitive. Perform the reset assertion and deassertion sequence at the i_csr_rst_n 0->1 edge.
- Resets the TX and RX MAC, TX and RX EMIB interface, Ethernet reconfiguration registers, PCS, and TX and RX PMA interfaces.
- This reset leads to deassertion of the o_tx_lanes_stable and o_rx_pcs_ready output signals.
- In Ethernet Toolkit, perform this reset using the Full System Reset.
In addition, the synchronous i_reconfig_reset signal resets the IP core transceiver reconfiguration interface, Ethernet reconfiguration interfaces, and some Ethernet soft registers. i_reconfig_reset signal is synchronous to the i_reconfig_clk and is positive edge triggered.
PMA reset is only required when you change any PMA settings. For PMA reset information, refer to PMA Reset and PMA Analog Reset in the E-Tile Transceiver PHY User Guide.
System Considerations
- You should perform a system reset before beginning IP core operation, preferably by asserting and deasserting the i_csr_rst_n/i_sl_csr_rst_n and i_reconfig_reset signals together. Alternatively, you can use eio_sys_rst 25 register instead of i_csr_rst_n/i_sl_csr_rst_n signals.
- To assert i_csr_rst_n/i_sl_csr_rst_n, drive the signal to 0. To deassert i_csr_rst_n/i_sl_csr_rst_n, drive the signal to 1.
- To assert i_reconfig_reset, drive the signal to 1. To deassert i_reconfig_reset, drive the signal to 0. You should access reconfiguration registers 32 µs after the deassertion of i_reconfig_reset.
- To assert eio_sys_rst, write 1'b1 to the 0x310[0] register. To deassert eio_sys_rst, write 1'b0 to the 0x310[0] register. The IP core implements the correct reset sequence to reset the entire IP core.
- For 10GE/25GE multi-channel master-slave configuration (with RS-FEC enabled), all channels must be taken out of the initial reset before each channel can start functioning independently. For more information, refer to Ethernet Adaptation Flow with Non-external AIB Clocking.
- For 10GE/25GE multi-channel non master-slave configuration (with RS-FEC disabled), the master/slave resets can be asserted/deasserted in any order for each of the individual channels.
- If you assert the transmit reset when the downstream receiver is already aligned, the receiver loses alignment. Before the downstream receiver loses lock, it might receive some malformed frames.
- If you assert the receive reset while the upstream transmitter is sending packets, the packets in transit are corrupted.