Visible to Intel only — GUID: xfn1519832056506
Ixiasoft
Visible to Intel only — GUID: xfn1519832056506
Ixiasoft
2.11.11. Deterministic Latency Interface
The E-Tile Hard IP for Ethernet Intel FPGA IP Deterministic Latency Interface is available when you turn on Include deterministic latency measurement interface for 10G/25G channels in 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP variation.
When setting is turned on, you can view the deterministic latency interface directly from the Stratix® 10 E-Tile Transceiver Native PHY.
Use the deterministic latency interface if you want to measure the latency of the datapath when running a stack that does not include MAC. Signal Name |
Width | Description |
---|---|---|
o_tx_dl_async_pulse[ch-1:0] | 1 | Asynchronous output pulse signal for the transmitter latency measurement 28 of the deterministic latency application. There is a start pulse and a stop pulse. |
o_sl_rx_dl_async_pulse[ch-1:0] | 1 | Asynchronous output pulse signal for the receiver latency measurement28 of the deterministic latency application. There is a start pulse and a stop pulse. |
i_sl_latency_sclk[ch-1:0] | 1 | Clock signal for latency measurement28 of the deterministic latency application. |
i_sl_tx_dl_measure_sel[ch-1:0] | 1 | Mux select signal for the transmitter latency measurement.28 1 is for the datapath latency. 0 is for the wire delay. |
i_sl_rx_dl_measure_sel[ch-1:0] | 1 | Mux select signal for the receiver latency measurement.28 1 is for the datapath latency. 0 is for the wire delay. |