Visible to Intel only — GUID: stq1597288753616
Ixiasoft
Visible to Intel only — GUID: stq1597288753616
Ixiasoft
2.11.17.3.6. 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode
When PTP is enabled, the external AIB clocking is inherently enabled. Do not enable External AIB clocking parameter in the Parameter Editor, it is unnecessary and redundant. In the Quartus® Prime Pro Edition software version 21.4 or later, the Enable external AIB clocking parameter is not available when the Enable IEEE 1588 PTP parameter is turned on.
Number of Ethernet Channels | Data Rate | Core Interface | External AIB Clocking |
---|---|---|---|
2 | 25.78125 Gbps | 64 bits | Disabled |
This use case covers a scenario when PTP is enabled and the PTP Accuracy Mode is set to Advanced Mode.
With PTP enabled, a PTP channel and its source clock called PTP clock becomes the master channel regardless of FEC configuration.
Number of Channels of 10G/25G | Clock Port | PTP Clock | Clock Connection Guideline |
---|---|---|---|
Single channel | i_sl_clk_tx i_sl_clk_rx i_sl_clk_tx_tod i_sl_clk_rx_tod |
o_clk_pll_div64[1] | Connect o_clk_pll_div64[1] to i_sl_clk_tx and i_sl_clk_rx. Connect o_clk_pll_div66 to i_sl_clk_tx_tod. Connect o_clk_rec_div66 to i_sl_clk_rx_tod. |
2 channels | i_sl_clk_tx[1:0] i_sl_clk_rx[1:0] i_sl_clk_tx_tod[1:0] i_sl_clk_rx_tod[1:0] |
o_clk_pll_div64[2] | Connect o_clk_pll_div64[2] to i_sl_clk_tx[1:0] and i_sl_clk_rx[1:0]. Connect o_clk_pll_div66[1:0] to i_sl_clk_tx_tod[1:0]. Connect o_clk_rec_div66[1:0] to i_sl_clk_rx_tod[1:0]. |
3 channels | i_sl_clk_tx[2:0] i_sl_clk_rx[2:0] i_sl_clk_tx_tod[2:0] i_sl_clk_rx_tod[2:0] |
o_clk_pll_div64[3] | Connect o_clk_pll_div64[3] to i_sl_clk_tx[2:0] and i_sl_clk_rx[2:0]. Connect o_clk_pll_div66[2:0] to i_sl_clk_tx_tod[2:0]. Connect o_clk_rec_div66[2:0] to i_sl_clk_rx_tod[2:0]. |
4 channels | i_sl_clk_tx[2:0] i_sl_clk_rx[2:0] i_sl_clk_tx_tod[3:0] i_sl_clk_rx_tod[3:0] |
o_clk_pll_div64[4] | Connect o_clk_pll_div64[4] to i_sl_clk_tx[3:0] and i_sl_clk_rx[3:0]. Connect o_clk_pll_div66[3:0] to i_sl_clk_tx_tod[3:0]. Connect o_clk_rec_div66[3:0] to i_sl_clk_rx_tod[3:0]. |
In addition, the advanced mode requires an IOPLL to provide a clock frequency of 114.285714 MHz to connect to i_clk_ptp_sample. The IOPLL must be a stable, free running clock with the reference frequency meeting the IOPLL reference clock requirement as specified in the Stratix® 10 Clocking and PLL User Guide. You can also use any existing IOPLL in the your design to generate this required clock frequency.
IOPLL Signals | Description |
---|---|
refclk | Any system clock that meets the reference clock requirement. The default frequency is 100 MHz. The minimum and maximum frequency value depends on the selected device. |
rst | Global/system reset |
locked | Logic reset |
outclk_0 | i_clk_ptp_sample |