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Ixiasoft
Visible to Intel only — GUID: nxl1519750821051
Ixiasoft
2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP Supported Features
The IP core is designed to the IEEE 802.3-2015 High Speed Ethernet Standard available on the IEEE website (www.ieee.org) and the 25G/50G Ethernet Specification, Draft 1.6 available from the 25 Gigabit Ethernet Consortium. The MAC provides cut-through frame processing to optimize latency, and supports full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets. All E-Tile Hard IP for Ethernet Intel® FPGA IP variations are in full-duplex mode.
Features | Description |
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PCS | Hard IP logic that interfaces seamlessly to E-Tile transceivers. |
CAUI external interface consisting of four transceiver lanes operating at 25.78125 Gbps. | |
CAUI-2 external interface with two transceiver lanes operating at 53.125 Gbps with PAM4 encoding | |
25G AUI external interface with 1 transceiver lane operating at 25.78125 Gbps | |
10G AUI external interface with 1 transceiver lane operating at 10.3125 Gbps | |
Supports CAUI-4 links based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes. | |
Supports customizable data rate PCS from 2.5 to 28 Gbps for protocols other than Ethernet. | |
Optional RS-FEC(528,514) or RS-FEC(544,514) for 25G and 100G variations. | |
Supports 10G, 25G, and 100G variations.
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RX Skew Variation tolerance that exceeds the IEEE 802.3-2015 High Speed Ethernet Standard Clause 80.5 requirements. | |
OTN | Optional 25GE constant bit rate (CBR); with TX and RX PCS66 bit encoding/decoding and scrambling/descrambling disabled.
Note: The E-Tile Hard IP for Ethernet Intel® FPGA IP provides support for the OTN feature. For further inquiries, contact your nearest Altera sales representative.
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Optional RS-FEC(528,514) or RS-FEC(544,514) for 25G and 100G variations. | |
Flexible Ethernet (FlexE) | Optional CBR; with TX and RX PCS66 bit encoding/decoding disabled and scrambling/descrambling enabled. |
Optional RS-FEC(528,514) or RS-FEC(544,514) for 25G and 100G variations. | |
PMA Direct Mode | Optional to switch from MAC+PCS to PMA only mode during run-time. |
Frame Structure Control | Support for jumbo packets. |
RX CRC pass-through control. | |
1000 bits RX PCS lane skew tolerance for 100G links, which exceeds the IEEE 802.3-2015 High Speed Ethernet Standard Clause 82.2.12 requirements. | |
Optional per-packet TX CRC generation and insertion. | |
Optional Deficit Idle Counter (DIC) options to maintain a finely controlled 8-byte, 10-byte, or 12-byte inter-packet gap (IPG) minimum average, or allow the user to drive the IPG from the client interface | |
RX and TX preamble pass-through options for applications that require proprietary user management information transfer. | |
Optional TX MAC source address insertion. | |
TX automatic frame padding to meet the 64-byte minimum Ethernet frame length on the Ethernet link. Optional per-packet disabling of this feature. | |
TX error insertion capability supports client invalidation of in-progress input to TX client interface. | |
Frame Monitoring and Statistics | RX CRC checking and error reporting. |
Optional RX strict Start Frame Delimiter (SFD) checking per IEEE specification. | |
Optional RX strict preamble checking per IEEE specification. | |
RX malformed packet checking per IEEE specification. | |
Received control frame type indication. | |
Statistics counters. | |
Snapshot feature for precisely timed capture of statistics counter values. | |
Optional fault signaling: detects and reports local fault and generates remote fault, with support for unidirectional link fault as defined in IEEE 802.3-2015 High Speed Ethernet Standard Clause 66. | |
Flow Control | Optional IEEE 802.3-2015 Ethernet Standard Clause 31 Ethernet flow control operation using the pause registers or pause interface. |
Optional priority-based flow control that complies with the IEEE Standard 802.1Q-2014—Amendment 17: Priority-based Flow Control. | |
Pause frame filtering control. | |
Software can dynamically toggle local TX MAC data flow to support selective input flow cut-off. | |
Precision Time Protocol (PTP) | Optional support for the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol (1588 PTP) (1588v2). |
1-step (1588v1 and 1588v2) and 2-step TX (1588v2) timestamps. | |
Support for PTP headers in a variety of frame formats, including Ethernet encapsulated, UDP in IPv4, and UDP in IPv6. | |
Support for Checksum Zero and Checksum extension byte calculations. | |
Support for Correction field operations. | |
Programmable extra latency. | |
Debug and testability | Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing. |
Optional parallel loopback (TX to RX) at the MAC or at the PCS for self-diagnostic testing. | |
Bit-interleaved parity error counters to monitor bit errors per PCS lane. | |
RX PCS error block counters to monitor errors during and between frames. | |
Malformed and dropped packet counters. | |
High BER detection to monitor link bit error rates over all PCS lanes. | |
Optional scrambled Idle test pattern generation and checking. | |
Snapshot feature for precisely timed capture of statistics counter values. | |
TX error insertion capability supports test and debug. | |
Support for Ethernet Link Inspector (ELI) tool to monitor an Ethernet link. | |
Support for Ethernet Tool Kit to monitor an Ethernet link. | |
User System Interface | Avalon® memory-mapped interface ( Avalon® -MM) to access the IP core control and status registers. |
Avalon® streaming interface ( Avalon® -ST) connects the MAC to client logic with the start of frame in the most significant byte (MSB) in MAC+PCS variations. Interface for 100G channel has 512 bits; the 10/25G channels use 64 bits when the MAC layer is enabled. | |
MII data path interface connects the PCS to client logic in PCS-only variations. Interface for 100G variants has 256 bits of data and 32 bits of control; interface for 10G/25G variants has 64 bits of data and 8 bits of control. | |
Hardware and software reset control. | |
Supports Synchronous Ethernet (SyncE) by providing a CDR recovered clock output signal to the device fabric. | |
Supports external source clock for EMIB interface for applications that requires switching transceiver line rate. |
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3-2015 High Speed Ethernet Standard.