Visible to Intel only — GUID: hco1423076416855
Ixiasoft
Visible to Intel only — GUID: hco1423076416855
Ixiasoft
3.1.2.7. Synchronization and Scheduling of Data with the Channel Signal
For more than a single data wire, it is not equal to the channel count on data wires, but specifies the synchronous channel data alignment across all the data wires. For example,
![](/content/dam/docs/us/en/683337/24-1/hco1423076410132.png)
For a single wire, the channel signal is the same as a channel count. However, for ChanWireCount > 1, the channel signal specifies the channel data separation per wire, rather than the actual channel number: it counts from 0 to ChanCycleCount –1 rather than 0 to ChanCount –1.
![](/content/dam/docs/us/en/683337/24-1/hco1423076412383.png)
The channel signal remains a single wire, not a wire for each data wire. It counts over 0 to ChanCycleCount –1.
![](/content/dam/docs/us/en/683337/24-1/hco1423076414724.png)