DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Public
Document Table of Contents

6.3.2.1. DDC Design Example Generated Files

DSP Builder creates a directory structure that mirrors the structure of your model. The root to this directory can be an absolute path name or as a relative path name; for a relative path name (such as ../rtl), the directory structure is relative to the MATLAB current directory.
Figure 51. Generated Directory Structure for the DDC Design Example
Note: Separate subdirectories exist corresponding to each hierarchical level in your design.
Table 15.  Generated Files for the DDC Design Example
File Description
rtl directory
demo_ddc.xml An XML file that describes the attributes of your model.
demo_ddc_entity.xml An XML file that describes the boundaries of the system (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets).
rtl\demo_ddc subdirectory
<block name>.xml An XML file containing information about each block in the advanced blockset which translates into HTML on demand for display in the MATLAB Help viewer and for use by the DSP Builder menu options.
demo_ddc.vhd This is the top-level testbench file. It may contain non-synthesizable blocks, and may also contain empty black boxes for Simulink blocks that are not fully supported.
demo_ddc.add.tcl This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the Quartus Prime project.
demo_ddc.qip This file contains all the assignments and other information DSP Builder requires to process the demo_ddc design example in the Quartus Prime software. The file includes a reference to the .qip file in the DDCChip subsystem hierarchy.
<block name>.vhd DSP Builder generates a VHDL file for each component in your model.
demo_ddc_DDCChip_entity.xml An XML file that describes the boundaries of the DDCChip subsystem as a black box (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets).
DDCChip.xml An XML file that describes the attributes of the DDCChip subsystem.
*.stm Stimulus files.
safe_path.vhd Helper function that ensures a pathname is read correctly in the Quartus Prime software.
safe_path_msim.vhd Helper function that ensures a pathname is read correctly in ModelSim.
rtl\demo_ddc\<subsystem> subdirectories
Separate subdirectories exist for each hierarchical level in your design. These subdirectories include additional .xml .vhd, qip and .stm files describing the blocks contained in each level. Also additional .do and .tcl files exist, which it automatically calls from the corresponding files in the top-level of your model.
<subsystem>_atb.do Script that loads the subsystem automatic testbench into ModelSim.
<subsystem>_atb.wav.do Script that loads signals for the subsystem automatic testbench into ModelSim.
<subsystem>/<block>/*.hex Intel format .hex files that initialize the RAM blocks in your design for either simulation or synthesis.
<subsystem>.sdc Design constraint file for TimeQuest support.
<subsystem>.tcl Use this Tcl file to setup a Quartus Prime project.
<subsystem>_hw.tcl A Tcl script that loads the generated hardware into Platform Designer.

To display a particular signal, attach a Simulink scope, regenerate, and resimulate.

Figure 52. Simulation Results in the ModelSim Wave Window for the DDC Design Example