DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Public
Document Table of Contents

4.4. Modifying the DSP Builder Fibonacci Design to Generate Vector Signals

Simulate the design.

Procedure

  1. In the Scope Design Outputs scope zoom in on the y axis to see the short Fibonacci cycle.
    Figure 42. Fibonacci Scope Design Outputs
  2. Copy the real input block, add a Simulink mux and connect to the Convert block.
  3. Edit the timing of the real1 block, for example [0 1 1 1 zeros(1,50)].