DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Public
Document Table of Contents

3.6.1.1.1. Running the Real-Time Hardware Verification Design Example

Procedure

  1. Open demo_sil_nco in MATLAB and generate RTL.
  2. Build the Platform Designer system incorporating the RTL generated in Step 1.
    You can find the PLL and JTAG-to-Avalon Bridge components in the Platform Designer IP Catalog. For information on integrating DSP Builder generated RTL into Platform Designer, refer to Integrating a DSP Builder Design to a System .
  3. Compile the Intel Quartus project containing the Platform Designer system and generate programming files
    1. You need to map clock and reset to an appropriate pin on your board.
  4. Program your board.
  5. Run demo_sil_nco_app in MATLAB to connect to hardware and control and visualize NCO output (System Console in MATLAB App to Implement GUI figure).
    1. Click Refresh to see available hardware.
    2. Click Connect to connect to the selected hardware.
    3. Type in the new frequency in to Update Frequency to see the frequency change on the plot.