DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 7/15/2024
Public
Document Table of Contents

14.6.6.2. Modifying the Finite State Machine Block Specification File

Procedure

  1. For a sticky bit, modify the Finite State Machine block specification file to:
    # finite state machine for a sticky bit
    require version 23.3
    inputs x
    netlist
    transitions Sticky : q
        state Start
            if (x) Next 1
        state Next
            default Next 1
    end
    
    The Finite State Machine block now behaves like a sticky bit. The output is logic low (0) until it receives a logic high (1) and from that cycle onwards always the output is logic high (1).
    Figure 136. Sticky Bit
  2. For a rising edge detector, modify the Finite State Machine specification file:
    # rising edge detection
    require version 23.3
    inputs x
    netlist
    transitions Rising : q
        state A
            if (x) B 1
        state B
            if (x) B 0
            if (~x) A 0
    end
    
    Figure 137. Rising EdgeIf the x-input is already at logic 1 in the first cycle, the output is high for that cycle too.
  3. Correct this behavior by introducing a third state:
    # rising edge detection corrected
    require version 23.3
    inputs x
    netlist
    transitions Rising : q
        state Initial
            if (~x) Low 1
            if (x) High 0
        state Low
            if (~x) Low 0
            if (x) High 1
        state High
            if (~x) Low 0
            if (x) High 0
    end
    
    Figure 138. Third State

    Whenever no if clause matches a pattern of inputs, the Finite State Machine block remains in the same state and all output ports are set to logic low (0).

  4. Shorten the FSM specification to:
    # rising edge detection corrected
    require version 23.3
    inputs x
    netlist
    transitions Rising : q
        state Initial
            if (~x) Low 1
            if (x) High 0
        state Low
            if (x) High 1
        state High
            if (~x) Low 0
    end
    
  5. Add a reset input to the sticky bit FSM:
    # resettable sticky bit
    require version 23.3
    inputs x r
    netlist
    transitions Sticky : q
        state Start
            if (~r & ~x) Start 0
            if (~r &  x) Next  1
            if ( r & ~x) Start 0
            if ( r &  x) Start 0
        state Next
            if (~r & ~x) Next  1
            if (~r &  x) Next  1
            if ( r & ~x) Start 0
            if ( r &  x) Start 0
    end
    
    The inputs line is now declaring two inputs, x and r. The state transitions use Boolean expressions to match each possible input pattern. This specification is verbose and you can shorten it by exploiting the following conventions:
    • The if clauses are in order. The first one that matches the input pattern determines the output values and which state to transition to.
    • If no Boolean expression matches, the Finite State Machine block remains in the same state and all outputs are set to zero
  6. Using these rules, abbreviate the Finite State Machine specification:
    # resettable sticky bit
    require version 23.3
    inputs x r
    netlist
    transitions Sticky : q
        state Start
            if (~r &  x) Next 1
        state Next
            if (r) Start 0
            default Next 1
    end
    
    Table 278.  Boolean Operators
    Operator Logical expression
    A & B And
    A ^ B Exclusive-Or
    A | B Or
    ~A Not(A)