Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

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ID 683310
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Standard Edition Reference Manual 2. Compiler 3. C Language and Library Support 4. Component Interfaces 5. Component Memories (Memory Attributes) 6. Loops in Components 7. Component Concurrency 8. Arbitrary Precision Math Support 9. Component Target Frequency 10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary A. Supported Math Functions B. Intel® HLS Compiler Standard Edition Reference Manual Archives C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler x
2.1. Intel® HLS Compiler Standard Edition Command Options 2.2. Using Libraries in Your Component 2.3. Compiler Interoperability 2.4. Intel® HLS Compiler Pipeline Approach
3. C Language and Library Support x
3.1. Supported C and C++ Subset for Component Synthesis 3.2. C and C++ Libraries 3.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
4. Component Interfaces x
4.1. Component Invocation Interface 4.2. Avalon® Streaming Interfaces 4.3. Avalon® Memory-Mapped Master Interfaces 4.4. Slave Interfaces 4.5. Component Invocation Interface Arguments 4.6. Unstable and Stable Component Arguments 4.7. Global Variables 4.8. Structs in Component Interfaces 4.9. Reset Behavior
4.1. Component Invocation Interface x
4.1.1. Scalar Parameters 4.1.2. Pointer and Reference Parameters 4.1.3. Interface Definition Example: Component with Both Scalar and Pointer Arguments
4.3. Avalon® Memory-Mapped Master Interfaces x
4.3.1. Memory-Mapped Master Testbench Constructor 4.3.2. Implicit and Explicit Examples of Describing a Memory Interface
4.4. Slave Interfaces x
4.4.1. Control and Status Register (CSR) Slave 4.4.2. Slave Memories
5. Component Memories (Memory Attributes) x
5.1. Static Variables
6. Loops in Components x
6.1. Loop Initiation Interval (ii Pragma) 6.2. Loop-Carried Dependencies (ivdep Pragma) 6.3. Loop Coalescing (loop_coalesce Pragma) 6.4. Loop Concurrency (max_concurrency Pragma) 6.5. Loop Unrolling (unroll Pragma)
7. Component Concurrency x
7.1. Serial Equivalence within a Memory Space or I/O 7.2. Concurrency Control (hls_max_concurrency Attribute)
8. Arbitrary Precision Math Support x
8.1. Declaring ac_int Data Types 8.2. Integer Promotion and ac_int Data Types 8.3. Debugging Your Use of the ac_int Data Type 8.4. Declaring ac_fixed Data Types 8.5. AC Data Types and Native Compilers
8.1. Declaring ac_int Data Types x
8.1.1. Important Usage Information on the ac_int Data Type
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary x
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments 10.2. Intel® HLS Compiler Standard Edition Header Files 10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros 10.4. Intel® HLS Compiler Standard Edition Keywords 10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only) 10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes 10.7. Intel® HLS Compiler Standard Edition Loop Pragmas 10.8. Intel® HLS Compiler Standard Edition Component Attributes 10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces 10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments 10.11. Intel® HLS Compiler Standard Edition Component Macros 10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces 10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces 10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces 10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
A. Supported Math Functions x
A.1. Math Functions Provided by the math.h Header File A.2. Math Functions Provided by the extendedmath.h Header File A.3. Math Functions Provided by the ac_fixed_math.h Header File
1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual

10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces

Use the stream_out object and template arguments to explicitly declare Avalon® Streaming (ST) output interfaces. You can also use the stream_out Function APIs.

Table 31.   Intel® HLS Compiler Standard Edition Streaming Output Interface Template Summary
Template Object or Argument Description
ihc::stream_out Streaming output interface from the component.
ihc::readylatency Specifies the number of cycles between when the ready signal is deasserted and when the input stream can no longer accept new inputs.
ihc::bitsPerSymbol Describes how the data is broken into symbols on the data bus.
ihc::usesPackets Exposes the startofpacket and endofpacket sideband signals on the stream interface.
ihc::usesReady Controls whether a ready signal is present.

ihc::stream_out Template Object

Syntax
ihc::stream_out<datatype, template arguments >
Valid Values
Any valid POD (plain old data) C++ datatype.
Default Value
N/A
Description
Streaming output interface from the component. The testbench can read from this buffer once the component returns.
To learn more, review the following tutorials:
  • <quartus_installdir>/hls/examples/tutorials/interfaces/ explicit_streams_buffer
  • <quartus_installdir>/hls/examples/tutorials/interfaces/ explicit_streams_packet_ready_valid
  • <quartus_installdir>/hls/examples/tutorials/interfaces/ mulitple_stream_call_sites

ihc::readylatency Template Argument

Syntax
ihc::readylatency<value>
Valid Values
Non-negative integer value (between 0-8)
Default Value
0
Description
The number of cycles between when the ready signal is deasserted and when the sink can no longer accept new inputs.

Conceptually, you can view this parameter as an almost ready latency on the input FIFO buffer for the data that associates with the stream.

ihc::bitsPerSymbol Template Argument

Syntax
ihc::bitsPerSymbol<value>
Valid Values
Positive integer value that evenly divides the data type size.
Default Value
Datatype size
Description
Describes how the data is broken into symbols on the data bus.

Data is always broken down in little endian order.

ihc::usesPackets Template Argument

Syntax
ihc::usesPackets<value>
Valid Values
true or false
Default Value
false
Description
Exposes the startofpacket and endofpacket sideband signals on the stream interface, which can be accessed by the packet based reads/writes.

ihc::usesReady Template Argument

Syntax
ihc::usesReady<value>
Valid Values
true or false
Default Value
true
Description
Controls whether a ready signal is present. If false, the downstream sink must be able to accept data on every cycle that valid is asserted. This is equivalent to changing the stream read calls to tryWrite and assuming that success is always true.

If set to false, readyLatency must be 0.

Intel® HLS Compiler Standard Edition Streaming Output Interface stream_out Function APIs

Table 32.   Intel® HLS Compiler Standard Edition Streaming Output Interface stream_out Function Call APIs
Function API Description
void write(T data) Blocking write call from the component
void write(T data, bool sop, bool eop)

Available only if usesPackets<true> is set.

Blocking write with out-of-band startofpacket and endofpacket signals.
bool tryWrite(T data) Non-blocking write call from the component. The return value represents whether the write was successful.
bool tryWrite(T data, bool sop, bool eop)

Available only if usesPackets<true> is set.

Non-blocking write with out-of-band startofpacket and endofpacket signals.

The return value represents whether the write was successful. That is, the downstream interface was pulling the ready signal high while the HLS component tried to write to the stream.

T read() Blocking read call to be used from the testbench to read back the data from the component
T read(bool &sop, bool &eop)

Available only if usesPackets<true> is set.

Blocking read call to be used from the testbench to read back the data from the component with out-of-band startofpacket and endofpacket signals.

Intel® HLS Compiler Streaming Output Interfaces Code Example

The following code example illustrates both stream_out declarations and stream_out function APIs. 
// Blocking write
void foo (ihc::stream_out<int> &a) {
  static int count = 0;
  for(int idx = 0; idx < 5; idx ++){
    a.write(count++); // Blocking write
  }
}

// Non-blocking write
void foo_nb (ihc::stream_out<int> &a) {
  static int count = 0;
  for(int idx = 0; idx < 5; idx ++){
    bool success = a.tryWrite(count++); // Non-blocking write
    if (success) {
      // write was successful
    }
  }
}

int main() {
  ihc::stream_out<int> a;
  foo(a); // or foo_nb(a);
  
  // copy output to an array
  int outputData[5];
  for (int i = 0; i < 5; i++) {
    outputData[idx] = a.read();
  }
}
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