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1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
4.1. Component Invocation Interface
4.2. Avalon® Streaming Interfaces
4.3. Avalon® Memory-Mapped Master Interfaces
4.4. Slave Interfaces
4.5. Component Invocation Interface Arguments
4.6. Unstable and Stable Component Arguments
4.7. Global Variables
4.8. Structs in Component Interfaces
4.9. Reset Behavior
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments
10.2. Intel® HLS Compiler Standard Edition Header Files
10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
10.4. Intel® HLS Compiler Standard Edition Keywords
10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only)
10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes
10.7. Intel® HLS Compiler Standard Edition Loop Pragmas
10.8. Intel® HLS Compiler Standard Edition Component Attributes
10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces
10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments
10.11. Intel® HLS Compiler Standard Edition Component Macros
10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces
10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces
10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces
10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
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10.8. Intel® HLS Compiler Standard Edition Component Attributes
Feature | Description |
---|---|
hls_max_concurrency | Request more copies of the component memory so that the component can run multiple invocations in parallel. |
hls_max_concurrency Component Attribute
- Syntax
- hls_max_concurrency(<N>)
- Description
-
In some cases, the concurrency of a component is limited to 1. This limit occurs when the generated hardware cannot be shared across component invocations. For example, when using component memories for a non-static variable.
You can use this attribute to request more copies of the component memory so that the component can run multiple invocations in parallel.
This attribute can accept any non-negative whole number, including 0.- Value greater than 0
- A value greater than 0 indicates how many copies of the component memory to instantiate as well as how many component invocations can be in flight at once.
- Value equal to 0
- Setting hls_max_concurrency to a value of 0 is useful in cases when there is no component memory but the component still has a poor dynamic loop initiation interval (II) even if you believe your component II should be 1. You can review the II for loops in your component in the high level design report.
To learn more, review the design example: <quartus_installdir>/hls/examples/inter_decim_filter.
- Example
-
hls_max_concurrency(2) component void foo(ihc::stream_in<int> &data_in, ihc::stream_out<int> &data_out) { int arr[N]; for (int i = 0; i < N; i++) { arr[i] = data_in.read(); } // Operate on the data and modify in place for (int i = 0; i < N; i++) { data_out.write(arr[i]); } }