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1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
4.1. Component Invocation Interface
4.2. Avalon® Streaming Interfaces
4.3. Avalon® Memory-Mapped Master Interfaces
4.4. Slave Interfaces
4.5. Component Invocation Interface Arguments
4.6. Unstable and Stable Component Arguments
4.7. Global Variables
4.8. Structs in Component Interfaces
4.9. Reset Behavior
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments
10.2. Intel® HLS Compiler Standard Edition Header Files
10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
10.4. Intel® HLS Compiler Standard Edition Keywords
10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only)
10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes
10.7. Intel® HLS Compiler Standard Edition Loop Pragmas
10.8. Intel® HLS Compiler Standard Edition Component Attributes
10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces
10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments
10.11. Intel® HLS Compiler Standard Edition Component Macros
10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces
10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces
10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces
10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
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7. Component Concurrency
The Intel® HLS Compiler assumes that you want a fully pipelined data path in your component. In the C++ implementation, think of a fully pipelined data path as calling a function multiple times before the first call has returned (see also and Intel HLS Compiler Pipeline Approach). The behavior of multiple component invocations within the synthesized data path is subject to the concurrency model, so the Intel® HLS Compiler might not be able to deliver a component with a component initiation interval (II) of 1, or even any pipelining.
The Intel® HLS Compiler provides you with the hls_max_concurrency component attribute to help you control the maximum concurrency of your component.