Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

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ID 683310
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Standard Edition Reference Manual 2. Compiler 3. C Language and Library Support 4. Component Interfaces 5. Component Memories (Memory Attributes) 6. Loops in Components 7. Component Concurrency 8. Arbitrary Precision Math Support 9. Component Target Frequency 10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary A. Supported Math Functions B. Intel® HLS Compiler Standard Edition Reference Manual Archives C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler x
2.1. Intel® HLS Compiler Standard Edition Command Options 2.2. Using Libraries in Your Component 2.3. Compiler Interoperability 2.4. Intel® HLS Compiler Pipeline Approach
3. C Language and Library Support x
3.1. Supported C and C++ Subset for Component Synthesis 3.2. C and C++ Libraries 3.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
4. Component Interfaces x
4.1. Component Invocation Interface 4.2. Avalon® Streaming Interfaces 4.3. Avalon® Memory-Mapped Master Interfaces 4.4. Slave Interfaces 4.5. Component Invocation Interface Arguments 4.6. Unstable and Stable Component Arguments 4.7. Global Variables 4.8. Structs in Component Interfaces 4.9. Reset Behavior
4.1. Component Invocation Interface x
4.1.1. Scalar Parameters 4.1.2. Pointer and Reference Parameters 4.1.3. Interface Definition Example: Component with Both Scalar and Pointer Arguments
4.3. Avalon® Memory-Mapped Master Interfaces x
4.3.1. Memory-Mapped Master Testbench Constructor 4.3.2. Implicit and Explicit Examples of Describing a Memory Interface
4.4. Slave Interfaces x
4.4.1. Control and Status Register (CSR) Slave 4.4.2. Slave Memories
5. Component Memories (Memory Attributes) x
5.1. Static Variables
6. Loops in Components x
6.1. Loop Initiation Interval (ii Pragma) 6.2. Loop-Carried Dependencies (ivdep Pragma) 6.3. Loop Coalescing (loop_coalesce Pragma) 6.4. Loop Concurrency (max_concurrency Pragma) 6.5. Loop Unrolling (unroll Pragma)
7. Component Concurrency x
7.1. Serial Equivalence within a Memory Space or I/O 7.2. Concurrency Control (hls_max_concurrency Attribute)
8. Arbitrary Precision Math Support x
8.1. Declaring ac_int Data Types 8.2. Integer Promotion and ac_int Data Types 8.3. Debugging Your Use of the ac_int Data Type 8.4. Declaring ac_fixed Data Types 8.5. AC Data Types and Native Compilers
8.1. Declaring ac_int Data Types x
8.1.1. Important Usage Information on the ac_int Data Type
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary x
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments 10.2. Intel® HLS Compiler Standard Edition Header Files 10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros 10.4. Intel® HLS Compiler Standard Edition Keywords 10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only) 10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes 10.7. Intel® HLS Compiler Standard Edition Loop Pragmas 10.8. Intel® HLS Compiler Standard Edition Component Attributes 10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces 10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments 10.11. Intel® HLS Compiler Standard Edition Component Macros 10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces 10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces 10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces 10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
A. Supported Math Functions x
A.1. Math Functions Provided by the math.h Header File A.2. Math Functions Provided by the extendedmath.h Header File A.3. Math Functions Provided by the ac_fixed_math.h Header File
1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual

6.1. Loop Initiation Interval (ii Pragma)

The initiation interval, or II, is the number of clock cycles between the launch of successive loop iterations. Use the ii pragma to direct the Intel® High Level Synthesis (HLS) Compiler to attempt to set the initiation interval (II) for the loop that follows the pragma declaration. If the compiler cannot achieve the specified II for the loop, then the compilation errors out.
You might want to increase the II of a loop to get an fMAX improvement in your component. A loop is a good candidate to have the ii pragma applied to increase its loop II if the loop meets any of the following conditions:
  • The loop is not critical to the throughput of your component.
  • The running time of the loop is small compared to other loops it might contain.

You can also apply the ii pragma to force a loop to an II of 1 and accept a possible fMAX penalty.

To specify a loop initiation interval for a loop, specify the pragma before the loop as follows: 
#pragma ii <desired_initiation_interval>
The <desired_initiation_interval> parameter is required and is an integer that specifies the number of clock cycles to wait between the beginning of execution of successive loop iterations.

Example

Consider a case where your component has two distinct sequential pipelineable loops: an initialization loop with a low trip count and a processing loop with a high trip count and no loop-carried memory dependencies. In this case, the compiler does not know that the initialization loop has a much smaller impact on the overall throughput of your design. If possible, the compiler attempts to pipeline both loops with an II of 1.

Because the initialization loop has a loop-carried dependence, it will have a feedback path in the generated hardware. To achieve an II with such a feedback path, some clock frequency might be sacrificed. Depending on the feedback path in the main loop, the rest of your design could have run at a higher operating frequency.

If you specify #pragma ii 2 on the initialization loop, you tell the compiler that it can be less aggressive in optimizing II for this loop. Less aggressive optimization allows the compiler to pipeline the path limiting the fmax and could allow your overall component design to achieve a higher fmax.

The initialization loop takes longer to run with its new II. However, the decrease in the running time of the long-running loop due to higher fmax compensates for the increased length in running time of the initialization loop.

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