Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

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ID 683310
Date 12/18/2019
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Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Standard Edition Reference Manual 2. Compiler 3. C Language and Library Support 4. Component Interfaces 5. Component Memories (Memory Attributes) 6. Loops in Components 7. Component Concurrency 8. Arbitrary Precision Math Support 9. Component Target Frequency 10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary A. Supported Math Functions B. Intel® HLS Compiler Standard Edition Reference Manual Archives C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler x
2.1. Intel® HLS Compiler Standard Edition Command Options 2.2. Using Libraries in Your Component 2.3. Compiler Interoperability 2.4. Intel® HLS Compiler Pipeline Approach
3. C Language and Library Support x
3.1. Supported C and C++ Subset for Component Synthesis 3.2. C and C++ Libraries 3.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
4. Component Interfaces x
4.1. Component Invocation Interface 4.2. Avalon® Streaming Interfaces 4.3. Avalon® Memory-Mapped Master Interfaces 4.4. Slave Interfaces 4.5. Component Invocation Interface Arguments 4.6. Unstable and Stable Component Arguments 4.7. Global Variables 4.8. Structs in Component Interfaces 4.9. Reset Behavior
4.1. Component Invocation Interface x
4.1.1. Scalar Parameters 4.1.2. Pointer and Reference Parameters 4.1.3. Interface Definition Example: Component with Both Scalar and Pointer Arguments
4.3. Avalon® Memory-Mapped Master Interfaces x
4.3.1. Memory-Mapped Master Testbench Constructor 4.3.2. Implicit and Explicit Examples of Describing a Memory Interface
4.4. Slave Interfaces x
4.4.1. Control and Status Register (CSR) Slave 4.4.2. Slave Memories
5. Component Memories (Memory Attributes) x
5.1. Static Variables
6. Loops in Components x
6.1. Loop Initiation Interval (ii Pragma) 6.2. Loop-Carried Dependencies (ivdep Pragma) 6.3. Loop Coalescing (loop_coalesce Pragma) 6.4. Loop Concurrency (max_concurrency Pragma) 6.5. Loop Unrolling (unroll Pragma)
7. Component Concurrency x
7.1. Serial Equivalence within a Memory Space or I/O 7.2. Concurrency Control (hls_max_concurrency Attribute)
8. Arbitrary Precision Math Support x
8.1. Declaring ac_int Data Types 8.2. Integer Promotion and ac_int Data Types 8.3. Debugging Your Use of the ac_int Data Type 8.4. Declaring ac_fixed Data Types 8.5. AC Data Types and Native Compilers
8.1. Declaring ac_int Data Types x
8.1.1. Important Usage Information on the ac_int Data Type
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary x
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments 10.2. Intel® HLS Compiler Standard Edition Header Files 10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros 10.4. Intel® HLS Compiler Standard Edition Keywords 10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only) 10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes 10.7. Intel® HLS Compiler Standard Edition Loop Pragmas 10.8. Intel® HLS Compiler Standard Edition Component Attributes 10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces 10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments 10.11. Intel® HLS Compiler Standard Edition Component Macros 10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces 10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces 10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces 10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
A. Supported Math Functions x
A.1. Math Functions Provided by the math.h Header File A.2. Math Functions Provided by the extendedmath.h Header File A.3. Math Functions Provided by the ac_fixed_math.h Header File
1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual

10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes

Use the component memory attributes to control the on-chip component memory architecture of your component.

Table 23.   Intel® HLS Compiler Standard Edition Component Memory Attributes Summary
Memory Attribute Description
hls_register Forces a variable or array to be carried through the pipeline in registers.

A register variable can be implemented either exclusively in flip-flops (FFs) or in a mix of FFs and RAM-based FIFOs.

hls_memory Forces a variable or array to be implemented as embedded memory.
hls_singlepump Specifies that the memory implementing the variable or array must be clocked at the same rate as the component accessing the memory.
hls_doublepump Specifies that the memory implementing the variable or array must be clocked at twice the rate as the component accessing the memory.
hls_numbanks Specifies that the memory implementing the variable or array must have a defined number of memory banks.
hls_bankwidth Specifies that the memory implementing the variable or array must have memory banks of a defined width.
hls_bankbits Forces the memory system to split into a defined number of memory banks and defines the bits used to select a memory bank.
hls_numports_readonly_writeonly

Specifies that the memory implementing the variable or array must have a defined number of read and write ports.

hls_simple_dual_port_memory Specifies that the memory implementing the variable or array should have no port that services both reads and writes.
hls_merge (depthwise) Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a depth-wise manner.
hls_merge (widthwise) Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a width-wise manner.
hls_init_on_reset Forces the static variables inside the component to be initialized when the component reset signal is asserted.
hls_init_on_powerup Sets the component memory implementing the static variable to initialize on power-up when the FPGA is programmed.
hls_max_concurrency Specifies the memory has a defined maximum number of private copies to allow concurrent iterations of a loop at any given time.

hls_register Memory Attribute

Syntax
hls_register
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces a variable or array to be implemented as registers.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/swap_vs_copy.

hls_memory Memory Attribute

Syntax
hls_memory
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces a variable or array to be implemented as embedded memory.

hls_singlepump Memory Attribute

Syntax
hls_singlepump
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must be clocked at the same rate as the component accessing the memory.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/QRD.

hls_doublepump Memory Attribute

Syntax
hls_doublepump
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must be clocked at twice the rate of the component accessing the memory.

hls_numbanks Memory Attribute

Syntax
hls_numbanks(N)
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must have N banks, where N is a power-of-two constant number.

hls_bankwidth Memory Attribute

Syntax
hls_bankwidth(N)
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must have banks that are N bytes wide, where N is a power-of-two constant number.

hls_bankbits Memory Attribute

Syntax
hls_bankbits(b 0 , b 1 , ..., b n )
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces the memory system to split into 2n+1 banks, with {b 0 , b 1 , ..., b n } forming the bank-select bits.
Important: b 0 , b 1 , ..., b n must be consecutive, positive integers. You can specify the consecutive, positive integers in ascending or descending order.

If you do not specify the hls_bankwidth(N) attribute along with this attribute, then b 0 , b 1 , ..., b n are mapped to array index bits 0 to n-1 in the memory bank implementation.

hls_numports_readonly_writeonly Memory Attribute

Syntax
hls_numports_readonly_writeonly(M, N)
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description

Specifies that the memory implementing the variable or array must have M read ports and N write ports, where M and N are constant numbers greater than zero.

hls_simple_dual_port_memory Memory Attribute

Syntax
hls_simple_dual_port_memory
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array should have no port that services both reads and writes.

hls_merge (depthwise) Memory Attribute

Syntax
hls_merge("mem_name", "depth")
Constraints
N/A
Default Value
N/A
Description
Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a depth-wise manner.

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/depth_wise_merge.

hls_merge (widthwise) Memory Attribute

Syntax
hls_merge("mem_name", "width")
Constraints
N/A
Default Value
N/A
Description
Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a width-wise manner.

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/width_wise_merge.

hls_init_on_reset Memory Attribute

Syntax
hls_init_on_reset
Constraints
N/A
Default Value
Default behavior for static variables.
Description
Forces the static variable inside the component to be initialized when the component reset signal is asserted. This requires an additional write port to the component memory implemented and can increase the power-up latency when the component is reset.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init.

hls_init_on_powerup Memory Attribute

Syntax
hls_init_on_powerup
Constraints
N/A
Default Value
N/A
Description
Sets the component memory implementing the static variable to initialize on power-up when the FPGA is programmed. When the component is reset, the component memory is not reset back to the initialized value of the static.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init.

hls_max_concurrency Memory Attribute

Syntax
hls_max_concurrency(N)
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory can have a maximum N private copies to allow N concurrent iterations of a loop at any given time, where N is rounded up to the nearest power of 2.

Apply this attribute only when the scope of a variable (through its declaration or access pattern) is limited to a loop. If the loop has the max_concurrency pragma applied to it, the number of private copies created is the lesser of the hls_max_concurrency memory attribute value and the max_concurrency pragma value.

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