Intel® High Level Synthesis Compiler Standard Edition: Reference Manual

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ID 683310
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Standard Edition Reference Manual 2. Compiler 3. C Language and Library Support 4. Component Interfaces 5. Component Memories (Memory Attributes) 6. Loops in Components 7. Component Concurrency 8. Arbitrary Precision Math Support 9. Component Target Frequency 10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary A. Supported Math Functions B. Intel® HLS Compiler Standard Edition Reference Manual Archives C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler x
2.1. Intel® HLS Compiler Standard Edition Command Options 2.2. Using Libraries in Your Component 2.3. Compiler Interoperability 2.4. Intel® HLS Compiler Pipeline Approach
3. C Language and Library Support x
3.1. Supported C and C++ Subset for Component Synthesis 3.2. C and C++ Libraries 3.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
4. Component Interfaces x
4.1. Component Invocation Interface 4.2. Avalon® Streaming Interfaces 4.3. Avalon® Memory-Mapped Master Interfaces 4.4. Slave Interfaces 4.5. Component Invocation Interface Arguments 4.6. Unstable and Stable Component Arguments 4.7. Global Variables 4.8. Structs in Component Interfaces 4.9. Reset Behavior
4.1. Component Invocation Interface x
4.1.1. Scalar Parameters 4.1.2. Pointer and Reference Parameters 4.1.3. Interface Definition Example: Component with Both Scalar and Pointer Arguments
4.3. Avalon® Memory-Mapped Master Interfaces x
4.3.1. Memory-Mapped Master Testbench Constructor 4.3.2. Implicit and Explicit Examples of Describing a Memory Interface
4.4. Slave Interfaces x
4.4.1. Control and Status Register (CSR) Slave 4.4.2. Slave Memories
5. Component Memories (Memory Attributes) x
5.1. Static Variables
6. Loops in Components x
6.1. Loop Initiation Interval (ii Pragma) 6.2. Loop-Carried Dependencies (ivdep Pragma) 6.3. Loop Coalescing (loop_coalesce Pragma) 6.4. Loop Concurrency (max_concurrency Pragma) 6.5. Loop Unrolling (unroll Pragma)
7. Component Concurrency x
7.1. Serial Equivalence within a Memory Space or I/O 7.2. Concurrency Control (hls_max_concurrency Attribute)
8. Arbitrary Precision Math Support x
8.1. Declaring ac_int Data Types 8.2. Integer Promotion and ac_int Data Types 8.3. Debugging Your Use of the ac_int Data Type 8.4. Declaring ac_fixed Data Types 8.5. AC Data Types and Native Compilers
8.1. Declaring ac_int Data Types x
8.1.1. Important Usage Information on the ac_int Data Type
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary x
10.1. Intel® HLS Compiler Standard Edition i++ Command-Line Arguments 10.2. Intel® HLS Compiler Standard Edition Header Files 10.3. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros 10.4. Intel® HLS Compiler Standard Edition Keywords 10.5. Intel® HLS Compiler Standard Edition Simulation API (Testbench Only) 10.6. Intel® HLS Compiler Standard Edition Component Memory Attributes 10.7. Intel® HLS Compiler Standard Edition Loop Pragmas 10.8. Intel® HLS Compiler Standard Edition Component Attributes 10.9. Intel® HLS Compiler Standard Edition Component Default Interfaces 10.10. Intel® HLS Compiler Standard Edition Component Invocation Interface Arguments 10.11. Intel® HLS Compiler Standard Edition Component Macros 10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces 10.13. Intel® HLS Compiler Standard Edition Streaming Output Interfaces 10.14. Intel® HLS Compiler Standard Edition Memory-Mapped Interfaces 10.15. Intel® HLS Compiler Standard Edition Arbitrary Precision Data Types
A. Supported Math Functions x
A.1. Math Functions Provided by the math.h Header File A.2. Math Functions Provided by the extendedmath.h Header File A.3. Math Functions Provided by the ac_fixed_math.h Header File
1. Intel® HLS Compiler Standard Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Intel® High Level Synthesis Compiler Standard Edition Compiler Reference Summary
A. Supported Math Functions
B. Intel® HLS Compiler Standard Edition Reference Manual Archives
C. Document Revision History of the Intel® HLS Compiler Standard Edition Reference Manual

4.4.2. Slave Memories

By default, component functions access parameters that are passed by reference through an Avalon® Memory-Mapped (MM) Master interface. An alternative way to pass parameters by reference is to use an Avalon® MM Slave interface, which exists inside the component.
Having a pointer argument generate an Avalon® MM Master interface on the component has two potential disadvantages:
  • The master interface has a single port. If the component has multiple load-store sites, arbitration on that port might create stallable logic.
  • Depending on the system in which the component is instantiated, other masters might use the memory bus while the component is running and create undesirable stalls on the bus.

Because a slave memory is internal to the component, the HLS compiler can create a memory architecture that is optimized for the access pattern of the component such as creating banked memories or coalescing memories.

Slave memories differ from component memories because they can be accessed from an Avalon® MM Master outside of the component. Component memories are by definition restricted to the component and cannot be accessed outside the component.

Unlike component memory, you cannot explicitly configure slave memory arguments (for example, banking or coalescing). You must rely on the automatic configurations generated by the compiler. You can control the structure of your slave memories only by restructuring your load and store operations.

Important: Reads and writes to slave memories from outside of the component should occur only when your component is not executing. You might experience undefined component behavior if outside slave memory accesses occur when your component is executing. The undefined behavior can occur even if a slave memory access is to a memory address that the component does not access.

A component can have many slave memory interfaces. Unlike slave register arguments that are grouped together in the CSR slave interface, each slave memory has a separate interface with separate data buses. The slave memory interface data bus width is determined by the width of the slave type. If the internal accesses to the memory have been coalesced, the slave memory interface data bus width might be a multiple of the width of the slave type.

Argument Label Description
hls_avalon_slave_memory_argument Implement the argument, in on-chip memory blocks, which can be read from or written to over a dedicated slave interface.
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